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PDF DS92LV3242 Data sheet ( Hoja de datos )

Número de pieza DS92LV3242
Descripción (DS92LV3241 / DS92LV3242) 20-85 MHz 32-Bit Channel Link II Serializer/Deserializer
Fabricantes National Semiconductor Corporation 
Logotipo National Semiconductor Corporation Logotipo



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DS92LV3241/DS92LV3242
September 17, 2009
20-85 MHz 32-Bit Channel Link II Serializer/Deserializer
General Description
The DS92LV3241 (SER) serializes a 32-bit data bus into 2 or
4 (selectable) embedded clock LVDS serial channels for a
data payload rate up to 2.72 Gbps over cables such as CATx,
or backplanes FR-4 traces. The companion DS92LV3242
(DES) deserializes the 2 or 4 LVDS serial data channels, de-
skews channel-to-channel delay variations and converts the
LVDS data stream back into a 32-bit LVCMOS parallel data
bus.
On-chip data Randomization/Scrambling and DC balance en-
coding and selectable serializer Pre-emphasis ensure a ro-
bust, low-EMI transmission over longer, lossy cables and
backplanes. The Deserializer automatically locks to incoming
data without an external reference clock or special sync pat-
terns, providing an easy “plug-and-lock” operation.
By embedding the clock in the data payload and including
signal conditioning functions, the Channel-Link II SerDes de-
vices reduce trace count, eliminate skew issues, simplify
design effort and lower cable/connector cost for a wide variety
of video, control and imaging applications. A built-in AT-
SPEED BIST feature validates link integrity and may be used
for system diagnostics.
Features
Wide Operating Range Embedded Clock SER/DES
Up to 32-bit parallel LVCMOS data
20 to 85 MHz parallel clock
Up to 2.72 Gbps application data paylod
Selectable Serial LVDS Bus Width
Dual Lane Mode (20 to 50 MHz)
Quad Lane Mode (40 to 85 MHz)
Simplified Clocking Architecture
No separate serial clock line
No reference clock required
Receiver locks to random data
On-chip Signal Conditioning for Robust Serial
Connectivity
Transmit Pre-Emphasis
Data randomization
DC-balance encoding
Receive channel deskew
Supports up to 10m CAT-5 at 2.7 Gbps
Integrated LVDS Terminations
Built-in AT-SPEED BIST for end-to-end system testing
AC-coupled interconnect for isolation and fault protection
> 4KV HBM ESD protection
Space-saving 64-pin TQFP package
Full industrial temperature range : -40° to +85°C
Applications
Industrial imaging (Machine-vision) and control
Security & Surveillance cameras and infrastructure
Medical imaging
Up to 30 bits per pixel, VGA to HD video transport and
display
www.DataSheet4U.com
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2009 National Semiconductor Corporation 301036
www.national.com

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DS92LV3242 pdf
DS92LV3241 Pin Diagram
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FIGURE 3. DS92LV3241 Pin Diagram— Top View
30103630
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DS92LV3242 arduino
Symbol
Parameter
Conditions
Min Typ
SERIALIZER SUPPLY CURRENT (DVDD*, PVDD* AND AVDD* PINS) *DIGITAL, PLL, AND ANALOG VDDS
IDDTQ
Serializer (Tx) Total Supply Current
Quad Mode
(includes load current)
f = 85 MHz,
CHECKER BOARD pattern
MODE = H,
VSEL = H,
PRE = OFF
150
f = 85 MHz,
CHECKER BOARD pattern
MODE = H,
VSEL = H,
150
RPRE = 12 k
f = 85 MHz,
RANDOM pattern
MODE = H,
VSEL = H,
PRE = OFF
140
f = 85 MHz,
RANDOM pattern
MODE = H,
VSEL = H,
140
RPRE = 12 k
IDDTD
Serializer (Tx) Total Supply Current
Dual Mode
(includes load current)
f= 50 MHz,
CHECKER BOARD pattern
MODE = L,
VSEL = H,
PRE = OFF
120
f= 50 MHz,
CHECKER BOARD pattern
MODE = H,
VSEL = H,
120
RPRE = 12 k
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f= 50 MHz,
RANDOM pattern
MODE = L,
VSEL = H,
PRE = OFF
115
f= 50 MHz,
RANDOM pattern
MODE = L,
VSEL = H,
115
RPRE = 12 k
IDDTZ
Serializer Supply Current
Power-down
TPWDNB = 0V
(All other LVCMOS Inputs = 0V)
2
Max Units
200
200
mA
195
195
145
145
mA
135
135
50 µA
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