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PDF PHP153NQ08LT Data sheet ( Hoja de datos )
| Número de pieza | PHP153NQ08LT | |
| Descripción | N-channel TrenchMOS logic level FET | |
| Fabricantes | NXP Semiconductors | |
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PHP/PHB153NQ08LT
N-channel TrenchMOS™ logic level FET
Rev. 01 — 31 March 2004
www.DataSheet4U.com
Product data
1. Product profile
1.1 Description
Logic level N-channel enhancement mode field-effect transistor in a plastic package
using TrenchMOS™ technology.
1.2 Features
s Logic level threshold
s Very low on-state resistance.
1.3 Applications
s Motors, lamps, solenoids
s DC-to-DC converters
s Uninterruptable power supplies
s General industrial applications.
1.4 Quick reference data
s VDS ≤ 75 V
s Ptot ≤ 300 W
s ID ≤ 75 A
s RDSon ≤ 5.5 mΩ.
2. Pinning information
Table 1: Pinning - SOT78 (TO-220AB) and SOT404 (D2-PAK), simplified outline and symbol
Pin Description
Simplified outline
Symbol
1 gate (g)
2 drain (d)
[1]
mb
mb
3 source (s)
mb mounting base;
connected to
drain (d)
g
MBB076
MBK106
123
SOT78 (TO-220AB)
2
1 3 MBK116
SOT404 (D2-PAK)
[1] It is not possible to make connection to pin 2 of the SOT404 package.
d
s
1 page  
Philips Semiconductors
www.DataSheet4U.com
PHP/PHB153NQ08LT
N-channel TrenchMOS™ logic level FET
6. Characteristics
Table 5: Characteristics
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Static characteristics
V(BR)DSS drain-source breakdown voltage
VGS(th) gate-source threshold voltage
IDSS drain-source leakage current
IGSS
RDSon
gate-source leakage current
drain-source on-state resistance
Conditions
ID = 250 µA; VGS = 0 V
Tj = 25 °C
Tj = −55 °C
ID = 1 mA; VDS = VGS; Figure 9
Tj = 25 °C
Tj = 175 °C
Tj = −55 °C
VDS = 75 V; VGS = 0 V
Tj = 25 °C
Tj = 175 °C
VGS = ±15 V; VDS = 0 V
VGS = 5 V; ID = 25 A; Figure 7 and 8
Tj = 25 °C
Tj = 175 °C
VGS = 4.5 V; ID = 25 A
VGS = 10 V; ID = 25 A; Figure 7 and 8
Min Typ Max Unit
75 - - V
68 - - V
1 1.5 2 V
0.5 - - V
- - 2.2 V
- - 1 µA
- - 500 µA
- 2 100 nA
- 5.2 6.1 mΩ
- 10.9 12.8 mΩ
- - 6.6 mΩ
- 4.7 5.5 mΩ
Dynamic characteristics
Qg(tot) total gate charge
Qgs gate-source charge
Qgd gate-drain (Miller) charge
Ciss input capacitance
Coss output capacitance
Crss reverse transfer capacitance
td(on)
turn-on delay time
tr rise time
td(off)
turn-off delay time
tf fall time
Source-drain diode
ID = 25 A; VDD = 60 V; VGS = 5 V; Figure 13
VGS = 0 V; VDS = 25 V; f = 1 MHz;
Figure 11
VDD = 30 V; RL = 1.2 Ω;
VGS = 5 V; RG = 5.6 Ω
VSD source-drain (diode forward) voltage IS = 25 A; VGS = 0 V; Figure 12
trr reverse recovery time
Qr recovered charge
IS = 20 A; dIS/dt = −100 A/µs;
VGS = 0 V; VR = 30 V
-
-
-
-
-
-
-
-
-
-
-
-
-
95 -
17 -
37 -
8770 -
840 -
335 -
68 -
144 -
273 -
116 -
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
0.8 1.2
68 -
176 -
V
ns
nC
9397 750 12721
Product data
Rev. 01 — 31 March 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
5 of 13
5 Page 
Philips Semiconductors
8. Revision history
Table 6: Revision history
Rev Date
CPCN
Description
01 20040331 -
Product data (9397 750 12721)
www.DataSheet4U.com
PHP/PHB153NQ08LT
N-channel TrenchMOS™ logic level FET
9397 750 12721
Product data
Rev. 01 — 31 March 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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