PDF DS92LV2421 Data sheet ( Hoja de datos )

Número de pieza	DS92LV2421
Descripción	24-bit Channel Link II Serializer and Deserializer
Fabricantes	National Semiconductor
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No Preview Available ! DS92LV2421/DS92LV2422 www.DataSheet4U.com PRELIMINARY May 25, 2010 10 to 75 MHz, 24-bit Channel Link II Serializer and Deserializer General Description The DS92LV2421 (Serializer) / DS92LV2422 (Deserializer) chipset translates a parallel 24–bit LVCMOS data interface into a single high-speed CML serial interface with embedded clock information. This single serial stream eliminates skew issues between clock and data, reduces connector size and interconnect cost for transferring a 24-bit or less, bus over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. In addition to the 24-bit data bus interface, the DS92LV2421 and DS92LV2422 also features a 3-bit control bus for slow speed signals. This allows implementing video and display applications with up to 24–bits per pixel (RGB), or embedding audio information with compressed video formats. Programmable transmit de-emphasis, receive equalization, on-chip scrambling and DC balancing enables longer dis- tance transmission over lossy cables and backplanes. The DS92LV2422 automatically locks to incoming data without an external reference clock or special sync patterns, providing easy “plug-and-go” operation. EMI is minimized by the use of low voltage differential signaling, receiver drive strength con- trol, and spread spectrum clocking capability. The DS92LV2421, DS92LV2422 chipset is programmable though an I2C interface as well as through pins. A built-in AT- SPEED BIST feature validates link integrity and may be used for system diagnostics. The DS92LV2421 is offered in a 48-pin LLP and the DS92LV2422 is offered in a 60-pin LLP package. Both de- vices operate over the full industrial temperature range of -40° C to +85°C. Features ■ 24–bit data, 3–bit control, 10 – 75 MHz clock ■ AC coupled STP interconnect cable up to 10 meters ■ Integrated terminations on Ser and Des ■ AT-SPEED link BIST mode and reporting pin ■ Optional I2C compatible Serial Control Bus ■ Power down mode minimizes power dissipation ■ 1.8V or 3.3V compatible LVCMOS I/O interface ■ -40° to +85°C temperature range ■ >8 kV HBM SERIALIZER — DS92LV2421 ■ Data scrambler for reduced EMI ■ DC-balance encoder for AC coupling ■ Selectable output VOD and adjustable de-emphasis DESERIALIZER — DS92LV2422 ■ FAST random data lock; no reference clock required ■ Adjustable input receiver equalization ■ LOCK (real time link status) reporting pin ■ EMI minimization on output parallel bus (SSCG) ■ Output Slew control (OS) Applications ■ Embedded Video and Display ■ Medical Imaging ■ Factory Automation ■ Office Automation — Printer, Scanner ■ Security and Video Surveillance ■ General purpose data communication Applications Diagram TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 2010 National Semiconductor Corporation 301101 30110127 www.national.com 1 page Pin Name Pin # I/O, Type Description www.DataSheet4U.com CONFIG [1:0] 13, 12 I, LVCMOS 00: Control Signal Filter DISABLED w/ pull-down 01: Control Signal Filter ENABLED 10: Reverse compatibility mode to interface with the DS90UR124 or DS99R124Q 11: Reverse compatibility mode to interface with the DS90C124 ID[x] 6 I, Analog I2C Serial Control Bus Device ID Address Select — Optional Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 10. SCL SDA BISTEN 8 I, LVCMOS I2C Serial Control Bus Clock Input - Optional SCL requires an external pull-up resistor to VDDIO. 9 I/O, LVCMOS I2C Serial Control Bus Data Input / Output - Optional Open Drain SDA requires an external pull-up resistor VDDIO. 31 I, LVCMOS BIST Mode — Optional w/ pull-down BISTEN = 0, BIST is disabled (normal operation) BISTEN = 1, BIST is enabled RES[2:0] 18, 16, 15 I, LVCMOS Reserved - tie LOW w/ pull-down Channel-Link II — CML Serial Interface DOUT+ 20 O, CML Non–Inverting Output. The output must be AC Coupled with a 0.1 µF capacitor. DOUT- 19 O, CML Inverting Output. The output must be AC Coupled with a 0.1 µF capacitor. Power and Ground VDDL 7 Power Logic Power, 1.8 V ±5% VDDP 14 Power PLL Power, 1.8 V ±5% VDDHS 17 Power TX High Speed Logic Power, 1.8 V ±5% VDDTX 22 Power Output Driver Power, 1.8 V ±5% VDDIO 30 Power LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10% GND DAP Ground DAP is the large metal contact at the bottom side, located at the center of the LLP package. Connect to the ground plane (GND) with at least 9 vias. NOTE: 1= HIGH, 0 L= LOW The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage. 5 www.national.com 5 Page Symbol Parameter Conditions www.DataSheet4U.com Pin/Freq. Min Typ Max Units IDDT1 IDDIOT1 IDDT2 IDDIOT2 Serializer Supply Current (includes load current) RL = 100 Ω, CLKIN = 75 MHz Checker Board VDD= 1.89V All VDD pins Pattern, VDDIO= 1.89V De-emph = 3kΩ, VODSEL = H, Figure 9 VDDIO = 3.6V VDDIO Checker Board VDD= 1.89V All VDD pins Pattern, VDDIO= 1.89V De-emph = 3kΩ, VODSEL = L, Figure 9 VDDIO = 3.6V VDDIO 65 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD mA mA mA mA mA mA IDDZ IDDIOZ Serializer Supply Current Power-down PDB = 0V , (All other LVCMOS Inputs = 0V) VDD= 1.89V VDDIO= 1.89V VDDIO = 3.6V All VDD pins VDDIO 40 1000 µA 5 10 µA 10 20 µA Deserializer DC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq. 3.3 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 3.0 to 3.6V VIH High Level Input Voltage VIL Low Level Input Voltage IIN Input Current VIN = 0V or VDDIO VOH High Level Output Voltage IOH = −0.5 mA, RDS = L VOL Low Level Output Voltage IOL = +0.5 mA, RDS = L PDB, BISTEN DO[23:0], CO1, CO2, CO3, CLKOUT, LOCK, PASS Output Short Circuit Current VOUT = 0V, RDS = L IOS Output Short Circuit Current VOUT = 0V, RDS = H VOUT = 0V, RDS = L VOUT = 0V, RDS = H PDB = 0V, OSS_SEL = 0V, IOZ TRI-STATE® Output Current VOUT = 0V or VDDIO 1.8 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 1.71 to 1.89V CLKOUT Outputs Outputs VIH High Level Input Voltage VIL Low Level Input Voltage PDB, BISTEN Min 2.0 GND −15 VDDIO- 0.2 −10 0.65* VDDIO GND IIN Input Current VIN = 0V or VDDIO VOH High Level Output Voltage IOH = −0.5 mA, RDS = L VOL Low Level Output Voltage IOL = +0.5 mA, RDS = L Output Short Circuit Current VOUT = 0V, RDS = L IOS Output Short Circuit Current VOUT = 0V, RDS = H VOUT = 0V, RDS = L VOUT = 0V, RDS = H IOZ TRI-STATE Output Current PDB = 0V, OSS_SEL = 0V, VOUT = 0V or VDDIO CML RECEIVER DC SPECIFICATIONS DO[23:0], CO1, CO2, CO3, CLKOUT, LOCK, PASS −15 VDDIO - 0.2 GND CLKOUT Outputs Outputs -10 Typ ±1 VDDIO GND TBD TBD TBD TBD ±1 VDDIO TBD TBD TBD TBD Max VDDIO 0.8 +15 0.2 +10 VDDIO 0.35* VDDIO +15 0.2 +10 Units V V μA V V mA mA mA mA µA V V μA V V mA mA mA mA µA 11 www.national.com 11 Page

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