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34AA02 데이터시트 PDF




Microchip Technology에서 제조한 전자 부품 34AA02은 전자 산업 및 응용 분야에서
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부품번호 34AA02 기능
기능 2K I2C Serial EEPROM Software Write-Protect
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34AA02 데이터시트, 핀배열, 회로
34AA02/34LC02
2K I2CSerial EEPROM Software Write-Protect
Features:
• Permanent and Resettable Software Write-Protect
for Lower Half of the Array (00h-7Fh)
• Single Supply with Operation Down to 1.7V
• Low-Power CMOS Technology:
- Read current 1 mA, typical
- Standby current, 100 nA, typical
• 2-Wire Serial Interface Bus, I2C™ Compatible
• Cascadable up to Eight Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Compatibility
• 1 MHz Clock for LC Versions
• Page Write Time 3 ms, typical
• Self-Timed Erase/Write Cycle
• 16-Byte Page Write Buffer
• ESD Protection > 4,000V
• Software Write Protection for Lower 128 Bytes
• Hardware Write Protection for Entire Array
• More than 1 Million Erase/Write Cycles
• Data Retention > 200 Years
• 8-Lead PDIP, SOIC, TSSOP, MSOP and TDFN
Packages
• 6-Lead SOT-23 Package
• Pb-free and RoHS Compliant
• Available for Extended Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
Device Selection Table
Part
Number
VCC
Range
Max. Clock
Frequency
34AA02
34LC02
1.7-5.5
2.2-5.5
400 kHz(1)
1 MHz
Note 1: 100 kHz for VCC <1.8V.
Temp
Ranges
I,E
I,E
www.DataSheet4U.com
Package Types
PDIP/SOIC/TSSOP/MSOP/TDFN
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
SOT-23
SCL 1
VSS 2
SDA 3
6 VCC
5 A0
4 A1
Description:
The Microchip Technology Inc. 34AA02/34LC02
(34XX02*) is a 2 Kbit Electrically Erasable PROM
capable of operation across a broad voltage range
(1.7V to 5.5V). This device has two software write-
protect features for the lower half of the array, as well
as an external pin that can be used to write-protect the
entire array. This allows the system designer to protect
none, half, or all of the array, depending on the
application. The device is organized as one block of
256 x 8-bit memory with a 2-wire serial interface. Low-
voltage design permits operation down to 1.7V, with
standby and active currents of only 100 nA and 1 mA,
respectively. The 34XX02 also has a page write
capability for up to 16 bytes of data. The 34XX02 is
available in the standard 8-pin PDIP, surface mount
SOIC, TSSOP, MSOP and TDFN packages. The
34XX02 is also available in the 6-lead, SOT-23
package.
*34XX02 is used in this document as a generic part number
for the 34AA02/34LC02 devices.
2011 Microchip Technology Inc.
DS22029F-page 1




34AA02 pdf, 반도체, 판매, 대치품
34AA02/34LC02
TABLE 1-2: AC SPECIFICATIONS
AC CHARACTERISTICS
VCC = +1.7V to +5.5V
Industrial (I): TA = -40°C to +85°C
Automotive (E):TA = -40°C to +125°C
Param.
No.
Symbol
Characteristic
Min.
Max. Units
Conditions
1
FCLK
Clock frequency
— 100 kHz 1.7V VCC < 1.8V
— 400
1.8V VCC 5.5V
— 1000
2.5V VCC 5.5V (34LC02)
2
THIGH
Clock high time
4000
600
500
— ns 1.7V VCC < 1.8V
— 1.8V VCC 5.5V
— 2.5V VCC 5.5V (34LC02)
3
TLOW
Clock low time
4700
1300
500
— ns 1.7V VCC < 1.8V
— 1.8V VCC 5.5V
— 2.5V VCC 5.5V (34LC02)
4 TR
SDA and SCL rise time (Note 1)
1000
ns 1.7V VCC < 1.8V
— 300
1.8V VCC 5.5V
— 300
2.5V VCC 5.5V (34LC02)
5 TF
SDA and SCL fall time (Note 1)
1000
ns 1.7V VCC < 1.8V
— 300
1.8V VCC 5.5V
— 300
2.5V VCC 5.5V (34LC02)
6 THD:STA Start condition hold time
4000
600
250
— ns 1.7V VCC < 1.8V
— 1.8V VCC 5.5V
— 2.5V VCC 5.5V (34LC02)
7 TSU:STA Start condition setup time
4700
600
250
— ns 1.7V VCC < 1.8V
— 1.8V VCC 5.5V
— 2.5V VCC 5.5V (34LC02)
8 THD:DAT Data input hold time
0 — ns (Note 2)
9 TSU:DAT Data input setup time
250 — ns 1.7V VCC < 1.8V
100 —
1.8V VCC 5.5V
100 —
2.5V VCC 5.5V (34LC02)
10 TSU:STO Stop condition setup time
4000
600
250
— ns 1.7V VCC < 1.8V
— 1.8V VCC 5.5V
— 2.5V VCC 5.5V (34LC02)
11
TSU:WP
WP setup time
4000
600
600
— ns 1.7V VCC < 1.8V
— 1.8V VCC 5.5V
— 2.5V VCC 5.5V (34LC02)
12 THD:WP WP hold time
4700
600
600
— ns 1.7V VCC < 1.8V
— 1.8V VCC 5.5V
— 2.5V VCC 5.5V (34LC02)
13 TAA
Output valid from clock (Note 2)
3500
ns 1.7V VCC < 1.8V
— 900
1.8V VCC 5.5V
— 400
2.5V VCC 5.5V (34LC02)
14
TBUF
Bus free time: Time the bus must be
1300
free before a new transmission can
4700
start
— ns 1.7V VCC < 1.8V
— 1.8V VCC 5.5V
— 2.5V VCC 5.5V (34LC02)
16 TSP
Input filter spike suppression
(SDA and SCL pins)
— 50 ns All except 34LC02
(Note 1 and Note 3)
17 TWC Write cycle time (byte or page)
— 5 ms —
18 —
Endurance
1M — cycles 25°C, VCC = 5.5V, Block mode
(Note 4)
www.DatNaoStheee1t4: UN.cootm100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the
falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppres-
sion. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult
the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.
DS22029F-page 4
2011 Microchip Technology Inc.

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34AA02 전자부품, 판매, 대치품
34AA02/34LC02
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
SCL
(B)
(D)
(D)
(C) (A)
SDA
Start
Condition
Address or
Data
Acknowledge Allowed
Valid
to Change
Stop
Condition
3.6 Device Addressing
A control byte is the first byte received following the
Start condition from the master device. The first part of
the control byte consists of a 4-bit control code which is
set to ‘1010’ for normal read and write operations and
0110’ for writing to the write-protect register. The
control byte is followed by three Chip Select bits (A2,
A1, A0). The Chip Select bits allow the use of up to
eight 34XX02 devices on the same bus and are used to
determine which device is accessed. The Chip Select
bits in the control byte must correspond to the logic lev-
els on the corresponding A2, A1 and A0 pins for the
device to respond.
For the SOT-23 package, the A2 pin is not connected.
During device addressing, the A2 Chip Select bit
(Figure 3-2) should be set to ‘0’. Only four 34XX02
SOT-23 packages can be connected to the same bus.
The eighth bit of slave address determines if the master
device wants to read or write to the 34XX02
(Figure 3-2). When set to a one, a read operation is
selected. When set to a zero, a write operation is
selected.
Operation
Read
Write
Write-Protect Register
Control Chip
Code Select
1010
1010
0110
A2 A1 A0
A2 A1 A0
A2 A1 A0
R/W
1
0
0
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FIGURE 3-2:
Start
CONTROL BYTE
ALLOCATION
Read/Write
Slave Address
R/W A
1 0 1 0 A2 A1 A0
OR
0 1 1 0 A2 A1 A0
4.0 WRITE OPERATIONS
4.1 Byte Write
Following the Start signal from the master, the device
code(4 bits), the Chip Select bits (3 bits) and the R/W
bit, which is a logic low, are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow,
once it has generated an Acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted
by the master is the word address and will be written
into the Address Pointer of the 34XX02.
After receiving another Acknowledge signal from the
34XX02, the master device will transmit the data word
to be written into the addressed memory location. The
34XX02 acknowledges again and the master generates
a Stop condition. This initiates the internal write cycle,
which means that during this time, the 34XX02 will not
generate Acknowledge signals (Figure 4-1). If an
attempt is made to write to the array when the software
or hardware write protection has been enabled, the
device will acknowledge the command, but no data will
be written. The write cycle time must be observed even
if the write protection is enabled.
2011 Microchip Technology Inc.
DS22029F-page 7

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