|
|
PDF 9LPRS525 Data sheet ( Hoja de datos )
| Número de pieza | 9LPRS525 | |
| Descripción | ICS9LPRS525 | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de 9LPRS525 (archivo pdf) en la parte inferior de esta página. Total 21 Páginas | ||
|
No Preview Available !
DATASHEET
56-pin CK505 for Intel Systems
ICS9LPRS525
Recommended Application:
56-pin CK505 compatible clock, w/fully integrated Vreg and series
resistors on differential outputs
Output Features:
• 2 - CPU differential low power push-pull pairs
• 7 - SRC differential push-pull pairs
• 1 - CPU/SRC selectable differential low power push-pull pair
• 1 - SRC/DOT selectable differential low power push-pull pair
• 1 - SRC/SE selectable differential push-pull pair/Single-ended
outputs
• 5 - PCI, 33MHz
• 1 - USB, 48MHz
• 1 - REF, 14.318MHz
Key Specifications:
• CPU outputs cycle-cycle jitter < 85ps
• SRC output cycle-cycle jitter < 125ps
• PCI outputs cycle-cycle jitter < 250ps
• +/- 100ppm frequency accuracy on all outputs
• SRC outputs meet PCIe Gen2 when sourced from PLL3
Features/Benefits:
• Supports spread spectrum modulation, 0 to -0.5% down
spread
• Supports CPU clks up to 400MHz
• Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
Table 1: CPU Frequency Select Table
FSLC2
B0b7
0
0
0
0
1
1
1
1
FSLB1
B0b6
0
0
1
1
0
0
1
1
FSLA1
B0b5
0
1
0
1
0
1
0
1
CPU
MHz
266.66
133.33
200.00
166.66
333.33
100.00
400.00
SRC PCI REF USB DOT
MHz MHz MHz MHz MHz
100.00 33.33 14.318 48.00 96.00
Reserved
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
Pin Configuration
PCI0/CR#_A 1
56 SCLK
VDDPCI 2
PCI1/CR#_B 3
PCI2/TME 4
PCI3/CFG0 5
PCI4/SRC5_EN 6
PCI_F5/ITP_EN 7
GNDPCI 8
VDD48 9
USB_48MHz/FSLA 10
GND48 11
VDD96IO 12
DOTT_96_LRS/SRCT0_LRS 13
DOTC_96_LRS/SRCC0_LRS 14
GND 15
VDD 16
SRCT1_LRS/SE1 17
SRCC1_LRS/SE2 18
GND 19
VDDPLL3IO 20
SRCT2_LRS/SATAT_LRS 21
SRCC2_LRS/SATAC_LRS 22
GNDSRC 23
SRCT3_LRS/CR#_C 24
SRCC3_LRS/CR#_D 25
VDDSRCIO 26
SRCT4_LRS 27
SRCC4_LRS 28
55 SDATA
54 REF0/FSLC/TEST_SEL
53 VDDREF
52 X1
51 X2
50 GNDREF
49 FSLB/TEST_MODE
48 CK_PWRGD/PD#
47 VDDCPU
46 CPUT0_LRS
45 CPUC0_LRS
44 GNDCPU
43 CPUT1_F_LRS
42 CPUC1_F_LRS
41 VDDCPUIO
40 NC
39 CPUT2_ITP_LRS/SRCT8_LRS
38 CPUC2_ITP_LRS/SRCC8_LRS
37 VDDSRCIO
36 SRCT7_LRS/CR#_F
35 SRCC7_LRS/CR#_E
34 GNDSRC
33 SRCT6_LRS
32 SRCC6_LRS
31 VDDSRC
30 PCI_STOP#/SRCT5_LRS
29 CPU_STOP#/SRCC5_LRS
56-SSOP & TSSOP
IDTTM PC MAIN CLOCK
1
1484C—04/20/10
1 page  
ICS9LPRS525
PC MAIN CLOCK
Absolute Maximum Ratings - DC Parameters
PARAMETER
SYMBOL
CONDITIONS
Maximum Supply Voltage
VDDxxx
Supply Voltage
Maximum Supply Voltage
VDDxxx_IO
Low-Voltage Differential I/O Supply
Maximum Input Voltage
Minimum Input Voltage
Storage Temperature
VIH
VIL
Ts
3.3V Inputs
Any Input
-
Case Temperature
Tc
Input ESD protection
ESD prot
Human Body Model
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied, nor guaranteed.
3 Maximum input voltage is not to exceed VDD
MIN
GND - 0.5
-65
2000
MAX
4.6
3.8
4.6
150
115
UNITS
V
V
V
V
°C
°C
V
Notes
7
7
4,5,7
4,7
4,7
4,7
6,7
Electrical Characteristics - Input/Supply/Common Output DC Parameters
PARAMETER
Ambient Operating Temp
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Low Threshold Input- High Voltage
Low Threshold Input- FSC = '1'
Voltage
Low Threshold Input- FSA,FSB = '1'
Voltage
Low Threshold Input-Low Voltage
PCI3/CFG0 Input
PCI3/CFG0 Input
PCI3/CFG0 Input
Input Leakage Current
Input Leakage Current
Output High Voltage
Output Low Voltage
Operating Supply Current
iAMT Mode Current
Powerdown Current
Input Frequency
Pin Inductance
Input Capacitance
Clk Stabilization
Tdrive_CR_off
Tdrive_CR_on
Tdrive_CPU
Tfall_SE
Trise_SE
SMBus Voltage
Low-level Output Voltage
Current sinking at VOLSMB = 0.4 V
SCLK/SDATA
Clock/Data Rise Time
SCLK/SDATA
Clock/Data Fall Time
Maximum SMBus Operating
Frequency
SYMBOL
Tambient
VDDxxx
VDDxxx_IO
VIHSE
VILSE
VIH_FS_TEST
VIH_FS_FSC
CONDITIONS
-
Supply Voltage
Low-Voltage Differential I/O Supply
Single-ended 3.3V inputs
Single-ended 3.3V inputs
3.3 V +/-5%
3.3 V +/-5%
VIH_FS_FSAB
VIL_FS
VIL_CFGHI
VIL_CFGMID
VIL_CFGLO
IIN
IINRES
VOHSE
VOLSE
IDDOP3.3
IDDOPIO
IDDiAMT3.3
IDDiAMTIO
IDDPD3.3
IDDPDIO
Fi
Lpin
CIN
COUT
CINX
TSTAB
TDRCROFF
TDRCRON
TDRSRC
TFALL
TRISE
VDD
VOLSMB
IPULLUP
TRI2C
TFI2C
FSMBUS
3.3 V +/-5%
3.3 V +/-5%
Optional input, 2.75V typ.
Optional input, 1.65V typ.
Optional input, 0.55V typ.
VIN = VDD , VIN = GND
Inputs with pull up or pull down resistors
VIN = VDD , VIN = GND
Single-ended outputs, IOH = -1mA
Single-ended outputs, IOL = 1 mA
Full Active, CL = Full load; Idd 3.3V
Full Active, CL = Full load; IDD IO
M1 mode, 3.3V Rail
M1 Mode, IO Rail
Power down mode, 3.3V Rail
Power down mode, IO Rail
VDD = 3.3 V
Logic Inputs
Output pin capacitance
X1 & X2 pins
From VDD Power-Up or de-assertion of PD to 1st
clock
Output stop after CR deasserted
Output run after CR asserted
CPU output enable after
PCI_STOP# de-assertion
Fall/rise time of all 3.3V control inputs from 20-80%
@ IPULLUP
SMB Data Pin
(Max VIL - 0.15) to
(Min VIH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
MIN
0
3.135
0.9975
2
VSS - 0.3
2
MAX UNITS
70 °C
3.465
V
3.465
V
VDD + 0.3
0.8
V
V
VDD + 0.3 V
0.7 1.5 V
0.7 VDD+0.3 V
VSS - 0.3
2.4
1.3
VSS - 0.3
-5
0.35
VDD+0.3
2
0.9
5
V
V
V
V
uA
-200 200 uA
2.4 V
0.4 V
115 mA
55 mA
36 mA
10 mA
5 mA
0.1 mA
15 MHz
7 nH
1.5 5 pF
6 pF
6 pF
1.8 ms
400 ns
0 us
10 ns
10 ns
10 ns
2.7 5.5 V
0.4 V
4 mA
1000
ns
300 ns
100 kHz
Notes
10
3
3
8
8
9, 10
9, 10
9, 10
2
1
1
10
10
IDTTM PC MAIN CLOCK
1484C—04/20/10
5
5 Page 
ICS9LPRS525
PC MAIN CLOCK
Table 3: IO_Vout select table
B9b2 B9b1 B9b0 IO_Vout
00
0 0.3V
00
1 0.4V
01
0 0.5V
01
1 0.6V
10
0 0.7V
10
1 0.8V
11
0 0.9V
11
1 1.0V
Table 4: Device ID table
B8b7 B8b6 B8b5 B8b4
Comment
000
0 56 pin TSSOP
Table 5: Slew Rate Selection Table
Bit 1 Bit 0
Slew Rate
00
HI-Z
0 1 0.7X (1.4V/ns)
1 0 0.8X (1.6 V/ns)
1 1 1X (2.0 V/ns)
Table 6. PCI3 Configuration Table
Note: 2 bits are needed since
CFG0 is tri-level input
SRC_Main_SE
PCI3/CFG0 PCI2/TME PCI3_CFG1 PCI3_CFG0
L
HW Strap HW Strap (Byte 11, bit 7) (Byte 11, bit 6) (Byte 0, bit 2) Config Mode
Low 0 or 1
0
0 0 0 = Default
Mid 0 or 1
0
1 11
High
TME=0
1
0 12
High
TME=1
1
1 13
Table 7. PLL Modes for PCI3 Configurations
Config
PLL1
PLL2
Mode
Outputs
SSC
Outputs
SSC
CPU/SRC/
0 = Default
PCI
Down
USB
NA
1
CPU
Down
USB
NA
2
CPU
Center
USB
NA
3
CPU
Center
USB/LAN25
NA
*Note: In Mode 3, Byte 8, bit (1:0) must be set to '1' to enable pin 17,18
PLL3
Outputs
SSC
-
SRC/PCI
SRC/PCI
SRC/PCI
-
Down
Down
Down
SRC1
PLL Source
PLL1
(Table 2
100MHz applies)
100MHz
PLL3
100MHz
PLL3
25MHz SE PLL2*
Table 8. ME Clock Selection Table
PCIF5/
ITP_EN iAMT_EN CPU2_AMT_EN CPU1_AMT_EN
Description
x1
0
0
Reserved
x1
0
1 Default, CPU1 = iAMT Clock
11
1
0 CPU2 = iAMT Clock
11
1
1 CPU1 and CPU2 both run in iAMT mode
IDTTM PC MAIN CLOCK
1484C—04/20/10
11
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet 9LPRS525.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 9LPRS525 | ICS9LPRS525 | Integrated Device Technology |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |