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AR6001X PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 AR6001X
기능 ROCm Single-Chip MAC/BB/Radio
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AR6001X 데이터시트, 핀배열, 회로
Data Sheet
PRELIMINARY
Revision December 2005
AR6001X ROCmTM Single-Chip MAC/BB/Radio for 2.4/5 GHz
Embedded WLAN Applications
General Description
The Atheros AR6001X is part of the AR6001
ROCm chipset family. It is a highly integrated,
all-CMOS, single chip solution for combined
cellular/handset applications and includes a 2.4/
5 GHz radio, analog-to-digital and digital-to-
analog converters, a baseband processor, multi-
protocol media access control (MAC), and a
MIPS CPU. It enables a high performance, cost
effective, low power, compact solution in a dual-
mode cellular/WLAN handset, PDA, VoIP
handset, or MP3/4 player.
The AR6001X’s transmitter combines baseband
in-phase (I) and quadrature (Q) signals, converts
them to the desired frequency, and drives the RF
signal off-chip. The receiver uses an integrated
dual-conversion architecture and requires no
off-chip intermediate frequency (IF) filters. The
frequency synthesizer supports one-MHz steps
to match the frequencies defined by IEEE 802.11
specifications. All internal clocks are generated
from a single external crystal.
The AR6001X implements half-duplex OFDM,
CCK, and DSSS baseband processing supporting
all IEEE 802.11a/g data rates. The MAC supports
the IEEE 802.11 wireless MAC protocol as well as
802.11i security, receive and transmit filtering,
error recovery, and quality of service (QoS).
The AR6001X provides multiple user interfaces
including UART, SDIO or SPI, and I2C. Other
external interfaces include serial EEPROM,
GPIOs, and LEDs.
AR6001X Features
All-CMOS single chip for IEEE 802.11a/g
compatible WLANs
Operates in 2.4 and 5 GHz frequency bands.
Freq
2.4 GHz
5 GHz
Bands
U-NII
ISM
DSRC
Europe
Japan
Frequency
2.312–2.472 GHz, 2.484 GHz
5.15–5.35 GHz, 5.725–5.825 GHz
5.725–5.850 GHz
5.850–5.925 GHz
5.15–5.35 GHz, 5.47–5.725 GHz
4.90–5.00 GHz, 5.03–5.091 GHz,
5.15–5.25, 5.25–5.35 GHz
Data rates of 6–54 Mbps for 802.11a and
1–54 Mbps for 802.11g
Integrated MIPS R4KEm CPU, clocked at up
to 141 MHz
4 KB D-cache and 8 KB I-cache
80 KB on-chip SRAM, 256 KB on-chip ROM
Stack-mounted 512 KB Flash
UART and serial EEPROM
Host interface support for SDIO/SPI, Local
Bus, or 16-bit PC Card interface
RTC support
Sleep clock using 32 KHz clock
Leading edge APSD support for energy
efficient operation
Bluetooth coexistence handshaking
IEEE 1149.1 standard test access port and
boundary scan architecture supported
Advanced power management to minimize
standby and active power
Standard 0.18 μm CMOS technology
216-ball, 10 mm x 10 mm BGA package
AR6001X ROCm Block Diagram
Aynchronous
Serial Interface
EEPROM/I2 S
LEDs/GPIO
I2C
AR6001
I$ D$
CPU
FLASH
DMA,
Timers,
Interrupts
Memory Control
RAM ROM
UART
SPI/Audio
GPIO
I2 C
MAC_CLK
MAC Baseband Radio
CORE_CLK
AHB
SDIO Interface
SDIO_CLK
SPI
Mem
Bridge
APB
Power, Clock
Management
LF_CLK
LDO
JTAG
REF_CLK
PA
LNA
SDIO or SPI Slave
16-bit Bus
32 KHz OSC or XTAL
1.1 – 1.8 V
Test, ICE
19.2/26/40/52 MHz
OSC or 40 MHz XTAL
© 2000-2005 by Atheros Communications, Inc. All rights reserved. Atheros™, 5-UP™, Driving the Wireless Future™, Atheros Driven™, Atheros Turbo
Mode™, and the Air is Cleaner at 5-GHz™ are trademarks of Atheros Communications, Inc. The Atheros logo is a registered trademark of
Atheros Communications, Inc. All other trademarks are the property of their respective holders.
Subject to change without notice.
COMPANY CONFIDENTIAL
1




AR6001X pdf, 반도체, 판매, 대치품
PRELIMINARY
(LDO_CONTROL) 59
7.1.12 Watchdog Timer
(WDT_CONTROL) 59
7.1.13 Watchdog Timer Interrupt Status
(WDT_STATUS) 59
7.1.14 Watchdog Timer Compare Tar-
get (WDT) 60
7.1.15 Watchdog Timer Current Count
(WDT_COUNT) 60
7.1.16 Watchdog Timer Reset
(WDT_RESET) 60
7.1.17 AR6001X CPU Interrupt Status
(INT_STATUS) 61
7.1.18 LF Timer 0 Compare Target
(LF_TIMER0) 61
7.1.19 LF Timer 0 Current Count
(LF_TIMER_COUNT0) 62
7.1.20 LF Timer 0 Control Bits
(LF_TIMER_CONTROL0) 62
7.1.21 LF Timer 0 Interrupt Status
(LF_TIMER_STATUS0) 62
7.1.22 LF Timer 1 Compare Target
(LF_TIMER1) 63
7.1.23 LF Timer 1 Current Count
(LF_TIMER_COUNT1) 63
7.1.24 LF Timer 1 Control Bits
(LF_TIMER_CONTROL1) 63
7.1.25 LF Timer 1 Interrupt Status
(LF_TIMER_STATUS1) 64
7.1.26 LF Timer 2 Compare Target
(LF_TIMER2) 64
7.1.27 LF Timer 2 Current Count
(LF_TIMER_COUNT2) 64
7.1.28 LF Timer 2 Control Bits
(LF_TIMER_CONTROL2) 65
7.1.29 LF Timer 2 Interrupt Status
(LF_TIMER_STATUS2) 65
7.1.30 LF Timer 3 Compare Target
(LF_TIMER3) 65
7.1.31 LF Timer 3 Current Count
(LF_TIMER_COUNT3) 66
7.1.32 LF Timer 3 Control Bits
(LF_TIMER_CONTROL3) 66
7.1.33 LF Timer 3 Interrupt Status
(LF_TIMER_STATUS3) 66
7.1.34 HF Timer Compare Target
(HF_TIMER) 66
7.1.35 HF Timer current count.
(HF_TIMER_COUNT) 67
7.1.36 Captured LF Timer Value Rela-
tive to HF Timer Read
(HF_LF_COUNT) 67
7.1.37 .HF Timer Control Bits
(HF_TIMER_CONTROL) 67
7.1.38 HF Timer Interrupt Status
(HF_TIMER_STATUS) 68
7.1.39 RTC Values Load into RTC Logic
(RTC_CONTROL) 68
7.1.40 RTC Time of Day
(RTC_TIME) 68
7.1.41 RTC Date and Year
(RTC_DATE) 69
7.1.42 RTC Set Time of Day
(RTC_SET_TIME) 69
7.1.43 RTC Set Date and Year
(RTC_SET_DATE) 69
7.1.44 RTC Alarm Time of Day
(RTC_SET_ALARM) 70
7.1.45 RTC Operation Configuration
(RTC_CONFIG) 70
7.1.46 RTC Alarm Enable, Set and Clear
(RTC_ALARM_STATUS) 71
7.1.47 UART Wakeup Events Enable
(UART_WAKEUP) 71
7.1.48 Reset Cause
(RESET_CAUSE) 71
7.1.49 System Sleep Status
(SYSTEM_SLEEP) 73
7.1.50 LDO_D Voltage
(LDO_VOLTAGE) 73
7.1.51 LDO_A Voltage
(LDO_A_VOLTAGE) 74
7.1.52 SDIO_LDO voltage
(SDIO_LDO_VOLTAGE) 74
7.1.53 Core Pad Enable
(CORE_PAD_ENABLE) 75
7.1.54 SDIO Signal Wrapper
(SDIO_WRAPPER) 75
7.1.55 MAC Sleep Options
(MAC_SLEEP_CONTROL) 75
7.1.56 Keep Awake Timer
(KEEP_AWAKE) 75
7.1.57 Chip Rev ID (CHIP_REV) 76
7.1.58 HF 32 KHz Clock Creation
(DERIVED_RTC_CLK) 76
7.1.59 Automatic Clock Gating Control
4 • AR6001X MAC/BB/Radio for Embedded WLAN Applications
4 December 2005
Atheros Communications, Inc.
COMPANY CONFIDENTIAL

4페이지










AR6001X 전자부품, 판매, 대치품
PRELIMINARY
7.6.22 Host CPU Interrupt
(INT_HOST) 128
7.6.23 Credit Counters Direct Access
(LOCAL_COUNT) 128
7.6.24 Credit Counter Atomic Incre-
ment (COUNT_INC) 128
7.6.25 Interface Scratch
(LOCAL_SCRATCH) 128
7.6.26 LB Configuration
(USE_LOCAL_BUS) 129
7.6.27 SDIO Configuration
(SDIO_CONFIG) 129
7.6.28 Stereo Block Configuration
(STEREO_CONFIG) 129
7.6.29 Set Stereo Volume
(STEREO_VOLUME) 130
7.6.30 Host Interface Access
(HOST_IF_WINDOW) 131
7.7 Host Interface Registers 131
7.7.1 Pending Interrupt Status
(HOST_INT_STATUS) 133
7.7.2 CPU-Sourced Interrupt Status
(CPU_INT_STATUS) 133
7.7.3 Error or Wakeup Interrupt Status
(ERROR_INT_STATUS) 133
7.7.4 Host IF Credit Counter Interrupt
(COUNTER_INT_STATUS) 13
4
7.7.5 Mailbox FIFO Status
(MBOX_FRAME) 134
7.7.6 Valid Bits for Lookahead
(RX_LOOKAHEAD_VALID) 1
34
7.7.7 Lookahead to Next 4 MBOX Rx0
FIFO Bytes
(RX_LOOKAHEAD0) 134
7.7.8 Lookahead to Next 4 MBOX Rx1
FIFO Bytes
(RX_LOOKAHEAD1) 136
7.7.9 Lookahead to Next 4 MBOX Rx2
FIFO Bytes
(RX_LOOKAHEAD2) 136
7.7.10 Lookahead to Next 4 MBOX Rx3
FIFO Bytes
(RX_LOOKAHEAD3) 136
7.7.11 Credit Counters Direct Access
(COUNT) 136
7.7.12 Credit Counter Atomic Decre-
ment (COUNT_DEC) 136
7.7.13 Interface Scratch
(SCRATCH) 137
7.7.14 HOST_INT_STATUS Enable Bits
(INT_STATUS_ENABLE) 137
7.7.15 CPU Sourced Interrupt Status
(CPU_INT_STATUS_ENABLE)
137
7.7.16 Error Interrupt Status
(ERROR_STATUS_ENABLE) 1
37
7.7.17 Credit Counter Interrupt Status
(COUNTER_INT_STATUS_EN
ABLE) 138
7.7.18 FIFO Timeout Period
(FIFO_TIMEOUT) 138
7.7.19 FIFO Timeout Enable.
(FIFO_TIMEOUT_ENABLE) 1
38
7.7.20 Disable Sleep Mode
(DISABLE_SLEEP) 138
7.7.21 LB Endianness
(LOCAL_BUS_ENDIAN) 139
7.7.22 LB and SPI Host Interface State
(LOCAL_BUS) 139
7.7.23 AR6001X CPU Interrupt
(INT_WLAN) 139
7.7.24 SPI Slave Interface Configuration
(SPI_CONFIG) 141
7.7.25 SPI Status (SPI_STATUS) 142
7.7.26 SDIO CIS Tuples Copy
(CIS_WINDOW) 143
8 Package Dimensions 145
9 Ordering Information 147
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR6001X MAC/BB/Radio for Embedded WLAN Applications • 7
December 2005 7

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AR6001X

ROCm Single-Chip MAC/BB/Radio

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