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PDF ATmega128A Data sheet ( Hoja de datos )
| Número de pieza | ATmega128A | |
| Descripción | 8-bit Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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ATmega128A
8-bit Microcontroller with 128Kbytes
In-System Programmable Flash
DATASHEET
Features
z High-performance, Low-power Atmel® AVR® 8-bit Microcontroller
z Advanced RISC Architecture
̶ 133 Powerful Instructions – Most Single Clock Cycle Execution
̶ 32 × 8 General Purpose Working Registers + Peripheral Control Registers
̶ Fully Static Operation
̶ Up to 16MHz Throughput at 16MIPS
̶ On-chip 2-cycle Multiplier
z High Endurance Non-volatile Memory segments
̶ 128Kbytes of In-System Self-programmable Flash program memory
̶ 4Kbytes EEPROM
̶ 4Kbytes Internal SRAM
̶ Write/Erase cycles: 10,000 Flash/100,000 EEPROM
̶ Data retention: 20 years at 85°C/100 years at 25°C(1)
̶ Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
̶ Up to 64 Kbytes Optional External Memory Space
̶ Programming Lock for Software Security
̶ SPI Interface for In-System Programming
z JTAG (IEEE std. 1149.1 Compliant) Interface
̶ Boundary-scan Capabilities According to the JTAG Standard
̶ Extensive On-chip Debug Support
̶ Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG
Interface
z Peripheral Features
̶ Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
̶ Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode
and Capture Mode
̶ Real Time Counter with Separate Oscillator
̶ Two 8-bit PWM Channels
̶ 6 PWM Channels with Programmable Resolution from 2 to 16 Bits
̶ Output Compare Modulator
̶ 8-channel, 10-bit ADC
• 8 Single-ended Channels
• 7 Differential Channels
• 2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
̶ Byte-oriented Two-wire Serial Interface
̶ Dual Programmable Serial USARTs
̶ Master/Slave SPI Serial Interface
Atmel-8151I-8-bit-AVR-ATmega128A_Datasheet-08/2014
1 page  
accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient
while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega128A provides the following features: 128 Kbytes of In-System Programmable Flash with Read-
While-Write capabilities, 4 Kbytes EEPROM, 4 Kbytes SRAM, 53 general purpose I/O lines, 32 general purpose
working registers, Real Time Counter (RTC), four flexible Timer/Counters with compare modes and PWM, 2
USARTs, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input
stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE
std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and
programming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the
SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves
the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or
Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a
timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O
modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In
Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows
very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator
and the Asynchronous Timer continue to run.
The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-chip ISP Flash
allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional
nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program
can use any interface to download the application program in the application Flash memory. Software in the
Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-
While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a
monolithic chip, the Atmel ATmega128A is a powerful microcontroller that provides a highly flexible and cost
effective solution to many embedded control applications.
The ATmega128A AVR is supported with a full suite of program and system development tools including: C
compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
2.2 ATmega103 and ATmega128A Compatibility
The ATmega128A is a highly complex microcontroller where the number of I/O locations supersedes the 64 I/O
locations reserved in the AVR instruction set. To ensure backward compatibility with the ATmega103, all I/O
locations present in ATmega103 have the same location in ATmega128A. Most additional I/O locations are
added in an Extended I/O space starting from $60 to $FF, (that is, in the ATmega103 internal RAM space).
These locations can be reached by using LD/LDS/LDD and ST/STS/STD instructions only, not by using IN and
OUT instructions. The relocation of the internal RAM space may still be a problem for ATmega103 users. Also,
the increased number of interrupt vectors might be a problem if the code uses absolute addresses. To solve
these problems, an ATmega103 compatibility mode can be selected by programming the fuse M103C. In this
mode, none of the functions in the Extended I/O space are in use, so the internal RAM is located as in
ATmega103. Also, the Extended Interrupt vectors are removed.
The Atmel®AVR®ATmega128A is 100% pin compatible with ATmega103, and can replace the ATmega103 on
current Printed Circuit Boards. The application note “Replacing ATmega103 by ATmega128A” describes what
the user should be aware of replacing the ATmega103 by an ATmega128A.
2.2.1
ATmega103 Compatibility Mode
By programming the M103C fuse, the ATmega128A will be compatible with the ATmega103 regards to RAM,
I/O pins and interrupt vectors as described above. However, some new features in ATmega128A are not
available in this compatibility mode, these features are listed below:
ATmega 128A [DATASHEET]
Atmel-8151I-8-bit-AVR-ATmega128A_Datasheet-08/2014
5
5 Page 
The ALU supports arithmetic and logic operations between registers or between a constant and a register.
Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is
updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the
whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address
contains a 16-bit or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and the Application Program
section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that
writes into the Application Flash Memory section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The
Stack is effectively allocated in the general data SRAM, and consequently the stack size is only limited by the
total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before
subroutines or interrupts are executed). The Stack Pointer – SP – is read/write accessible in the I/O space. The
data SRAM can easily be accessed through the five different addressing modes supported in the AVR
architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit
in the Status Register. All interrupts have a separate interrupt vector in the interrupt vector table. The interrupts
have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher
the priority.
The I/O memory space contains 64 addresses which can be accessed directly, or as the Data Space locations
following those of the Register file, $20 - $5F. In addition, the ATmega128A has Extended I/O space from $60 -
$FF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.
6.3 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers.
Within a single clock cycle, arithmetic operations between general purpose registers or between a register and
an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and
bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both
signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.
6.4 Status Register
The Status Register contains information about the result of the most recently executed arithmetic instruction.
This information can be used for altering program flow in order to perform conditional operations. Note that the
Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in
many cases remove the need for using the dedicated compare instructions, resulting in faster and more
compact code.
The status register is not automatically stored when entering an interrupt routine and restored when returning
from an interrupt. This must be handled by software.
ATmega 128A [DATASHEET]
Atmel-8151I-8-bit-AVR-ATmega128A_Datasheet-08/2014
11
11 Page | ||
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| PDF Descargar | [ Datasheet ATmega128A.PDF ] | |
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