Datasheet.kr   

Pm25LV010A PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 Pm25LV010A
기능 Serial Flash Memory
제조업체 Programmable Microelectronics
로고 Programmable Microelectronics 로고 


전체 30 페이지

		

No Preview Available !

Pm25LV010A 데이터시트, 핀배열, 회로
FEATURES
Pm25LV512A / 010A / 020 / 040
512 Kbit /1 Mbit / 2 Mbit / 4 Mbit 3.0 Volt-only,
Serial Flash Memory With 100 MHz SPI Bus Interface
Single Power Supply Operation
- Low voltage range: 2.7 V - 3.6 V
• Memory Organization
- Pm25LV512A: 64K x 8 (512 Kbit)
- Pm25LV010A: 128K x 8 (1 Mbit)
- Pm25LV020: 256K x 8 (2 Mbit)
- Pm25LV040: 512K x 8 (4 Mbit)
Cost Effective Sector/Block Architecture
- 512Kb : Uniform 4Kbyte sectors / Two uniform
32Kbyte blocks
- 1Mb : Uniform 4Kbyte sectors / Four uniform
32Kbyte blocks
- 2Mb : Uniform 4Kbyte sectors / Four uniform
64Kbyte blocks
- 4Mb : Uniform 4Kbyte sectors / Eight uniform
64Kbyte blocks
- Bottom sector is configurable as one 4Kbyte sector
or four 1Kbyte sectors (except Pm25LV512A)
Serial Peripheral Interface (SPI) Compatible
- Supports SPI Modes 0 (0,0) and 3 (1,1)
- Maximum 33 MHz clock rate for normal read
- Maximum 100 MHz clock rate for fast read
Page Program (up to 256 Bytes) Operation
- Typical 2 ms per page program
Sector, Block or Chip Erase Operation
- Typical 60 ms sector, block or chip erase
Software Write Protection
- The Block Protect (BP2, BP1, BP0) bits allow partial
or entire memory to be configured as read-only
Hardware Write Protection
- Protect and unprotect the device from write operation
by Write Protect (WP#) Pin
Low Power Consumption
- Typical 10 mA active read current
- Typical 15 mA program/erase current
High Product Endurance
- Guarantee 200,000 program/erase cycles per single
sector
- Minimum 20 years data retention
Industrial Standard Pin-out and Package
- 8-pin 150mil SOIC
- 8-pin 208mil SOIC for Pm25LV040
- 8-pin 300mil PDIP for Pm25LV040
- 8-contact WSON
- 8-pin TSSOP for Pm25LV512A
GENERAL DESCRIPTION
The Pm25LV512A/010A/020/040 are 512Kbit/1 Mbit/2 Mbit/4 Mbit 3.0 Volt-only Serial Peripheral Interface (SPI)
Flash memories. The devices are designed to support 33 MHz fastest clock rate in the industry in normal read
mode, 100 MHz in fast read mode and the bottom 4 Kbyte sector into four smaller 1 Kbyte sectors features(except
Pm25LV512A). The devices use a single low voltage, ranging from 2.7 Volt to 3.6 Volt, power supply to perform
read, erase and program operations. The devices can be programmed in standard EPROM programmers as well.
The Pm25LV512A/010A is backward compatible to their predecessors Pm25LV512/010.
The Pm25LV512A/010A/020/040 are accessed through a 4-wire SPI Interface consists of Serial Data Input (Sl),
Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. The devices support page program
mode, 1 to 256 bytes data can be programmed into the memory in one program operation. The memory of
Pm25LV512A/010A is divided into uniform 4 Kbyte sectors or uniform 32 Kbyte blocks (sector group - consists of
eight adjacent sectors) for data or code storage. The memory of Pm25LV020/040 are divided into uniform 4 Kbyte
sectors or uniform 64 Kbyte blocks (sector group - consists of sixteen adjacent sectors). The devices have an
innovative feature to configure the bottom 4 Kbyte sector into four smaller 1 Kbyte sectors for eliminating additional
serial EEPROM needed for storing data. This is a further cost reduction for overall system.
The Pm25LV512A/010A/020/040 are manufactured on pFLASH™’s advanced nonvolatile technology. The devices
are offered in 8-pin SOIC, 8-contact WSON and 8-pin PDIP (Pm25LV040) packages with operation frequency up to
100 MHz in fast read and 33 MHz in normal read mode.
Chingis Technology Corporation
1 Issue Date: Feb., 2009, Rev: 3.5




Pm25LV010A pdf, 반도체, 판매, 대치품
BLOCK DIAGRAM
Pm25LV512A/010A/020/040
Control Logic
Status
Register
CE#
SCK
WP#
SI
SO
HOLD#
Address Latch
& Counter
High Voltage Generator
I/O Buffers and
Data Latches
256 Bytes
Page Buffer
Y-DECODER
Memory Array
Chingis Technology Corporation
4 Issue Date: Feb., 2009, Rev: 3.5

4페이지










Pm25LV010A 전자부품, 판매, 대치품
REGISTERS (CONTINUED)
Pm25LV512A/010A/020/040
CONFIGURATION REGISTER (Pm25LV010A/020/ 040)
The Configuration Register is built by latchs need to be
set each time after power-up before enabling the 1 Kbyte
smaller sector size and 1 Kbyte sector write protection.
The Bit 0 - Bit 7 of Configuration Register are set as “0”s
after power-up reset. Therefore, the devices will be al-
ways set as normal mode - the bottom sector set as 4
Kbyte by default after power-up to maintain the back-
ward-compatibility.
The function of Configuration Register is described as
following:
The BP0, BP1, BP2, and SRWD are non-volatile memory
cells that can be written by Write Status Register (WRSR)
instruction. The default value of BP0, BP1, BP2, and
SRWD bits were set as “0” at factory. Once those bits
are written as “0” or “1”, it will not be changed by devices
power-up or power-down until next WRSR instruction al-
ters its value. The Status Register can be read by Read
Status Register (RDSR) instruction for its value and sta-
tus. Refer to Table 8 for Instruction Set.
The function of Status Register is described as following:
SCFG bit: The 1 Kbyte smaller sector mode is enabled
by writing “1” to SCFG bit, then Sector 0 is configured
as Sector 0_0, Sector 0_1, Sector 0_2 and Sector 0_3.
A Sector Erase (SECTOR_ER) instruction can be used
to erase any one of those four 1 Kbyte sectors. The
SCFG bit will be reset “0” state automatically at power
on stage. Thus, the 1 Kbyte smaller sector mode is
disabled at power on till SCFG bit was set.
The SCFG bit only can be enabled to “1” when BP0,
BP1&BP2 of status register were “1” state which in pro-
tection mode. On the other word, SCFG bit will be cleared
to “0” state when BPx were “0” to disable the protection
mode.
SP0_x bits: The write protection to those four 1 Kbyte
sectors can be activated by writing “1”s to the SP0_0,
SP0_1, SP0_2 and SP0_3 bits. The 1 Kbyte sector write
protection function can only be enabled when the SCFG
is also enabled.
The Write Configuration Register (WRCR) instruction can
be used to write “0”s or “1”s into Configuration Register.
And the Read Configuration Register (RDCR) instruc-
tion can be used to read the setting of Configuration
Register. Refer to Table 8 for Instruction Set.
STATUS REGISTER
The Status Register contains WIP and WEL status bits
to indicate the status of the devices, the Block Protec-
tion Bits (BP0, BP1 and BP2 (Pm25LV040 only)) to
define the portion of memory blocks to be write protected,
and SRWD control bits to be set for status register write
protection. Refer to Table 3 and Table 4 for Status Reg-
ister Format and Status Register Bit Definition.
WIP bit: The Write In Progress (WIP) bit can be used to
detact the progress or completion of program or erase
operation. When WIP bit is “0”, the devices are ready for
write status register, program or erase operation. When
WIP bit is “1”, the devices are busy.
WEL bit: The Write Enable Latch (WEL) bit indicates
the status of internal write enable latch. When WEL bit
is “0”, the write enable latch is disabled, all write opera-
tions include write status register, write configuration reg-
ister, page program, sector erase, block and chip erase
operations are inhibited. When WEL bit is “1”, the write
enable latch is enabled. Then write operations are allowed.
The WEL bit is enabled by Write Enable (WREN) instruc-
tion. All write register, program and erase instructions
must be preceded by a WREN instruction every time.
The WEL bit can be disabled by Write Disable (WRDI)
instruction or automatically return to reset state after the
completion of a write instruction.
BP2, BP1, BP0 bits: The Block Protection (BP2
(Pm25LV040 only), BP1, BP0) bits are used to define
the portion of memory area to be protected. Refer to Table
5 and Table 6 Block Write Protection Bits Setting for
Pm25LV512A/010A/020 and Pm25LV040. When one of
the combination of BP2, BP1 and BP0 bits were set as
“1”, the relevant memory area is protected. Any program
or erase operation to that area will be prohibited.
Especially, the Chip Erase (CHIP_ER) instruction is ex-
ecuted only if all the Block Protection Bits are set as
“0”s.
If SCFG bit was enabled to support 1KB x4 sectores on
Sector 0, Sector 0’s protection status will respect SP0_x
in Configuration Register and ignore BPx bits status
whatever protection status.
Chingis Technology Corporation
7 Issue Date: Feb., 2009, Rev: 3.5

7페이지



구       성총 30 페이지
다운로드[ Pm25LV010A.PDF 데이터시트 ]
구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

전력 반도체 판매 ( IGBT, TR 모듈, SCR, 다이오드 모듈 )

휴대전화 : 010-3582-2743


상호 : 아이지 인터내셔날

전화번호 : 051-319-2877, [ 홈페이지 ]



링크공유

링크 :

관련 데이터시트

부품번호상세설명 및 기능제조사
PM25LV010

(PM25LV010 / PM25LV512) Serial Flash Memory

Programmable Microelectronics
Programmable Microelectronics
PM25LV010

(PM25LV010 / 020 / 040) Serial Flash Memory

PMC
PMC

DataSheet.kr    |   2019   |  연락처   |  링크모음   |   검색  |   사이트맵