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PDF SZESD8006MUTAG Data sheet ( Hoja de datos )
| Número de pieza | SZESD8006MUTAG | |
| Descripción | ESD Protection Diode | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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ESD8006
ESD Protection Diode
Low Capacitance Array for High Speed
Data Lines
The ESD8006 is specifically designed to protect USB 3.0 and
Thunderbolt interfaces from ESD. Ultra−low capacitance and low
ESD clamping voltage make this device an ideal solution for
protecting voltage sensitive high speed data lines. The flow−through
style package allows for easy PCB layout and matched trace lengths
necessary to maintain consistent impedance between high speed
differential lines.
Features
• Low Capacitance (0.25 pF Max, I/O to GND)
• Protection for the Following IEC Standards:
IEC 61000−4−2 (Level 4)
• Low ESD Clamping Voltage
• SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
• USB 3.0/3.1
• Thunderbolt
• Display Port
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Operating Junction Temperature Range TJ −55 to +125 °C
Storage Temperature Range
Tstg − 55 to +150 °C
Lead Solder Temperature −
Maximum (10 Seconds)
TL 260 °C
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
ESD
ESD
±15 kV
±15 kV
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
www.onsemi.com
MARKING
DIAGRAM
UDFN8
CASE 517CB
1
6TMG
G
6T = Specific Device Code
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONFIGURATION
GND
10
GND
9
123456 78
I/O I/O GND I/O I/O GND I/O I/O
ORDERING INFORMATION
Device
Package
Shipping
ESD8006MUTAG
UDFN8 3000 / Tape &
(Pb−Free)
Reel
SZESD8006MUTAG UDFN8 3000 / Tape &
(Pb−Free)
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
See Application Note AND8308/D for further description of
survivability specs.
© Semiconductor Components Industries, LLC, 2015
February, 2015 − Rev. 4
1
Publication Order Number:
ESD8006/D
1 page  
ESD8006
VC = VHOLD + (IPP * RDYN)
NOTE:
VC, VOLTAGE (V)
Figure 6. Positive TLP I−V Curve
VC, VOLTAGE (V)
Figure 7. Negative TLP I−V Curve
TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns. VIEC is the equivalent voltage
stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description
below for more information.
Transmission Line Pulse (TLP) Measurement
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 8. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 9 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels. For more information
on TLP measurements and how to interpret them please
refer to AND9007/D.
L
50 W Coax
Cable
S Attenuator
÷
50 W Coax
Cable
10 MW
IM VM
VC DUT
Oscilloscope
Figure 8. Simplified Schematic of a Typical TLP
System
Figure 9. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
www.onsemi.com
5
5 Page 
ESD8006
Latch-Up Considerations
ON Semiconductor’s 8000 series of ESD protection
devices utilize a snap-back, SCR type structure. By using
this technology, the potential for a latch-up condition was
taken into account by performing load line analysis of
common high speed serial interfaces. Example load lines for
latch-up free applications and applications with the potential
for latch-up are shown below with a generic IV
characteristic of a snapback, SCR type structured device
overlaid on each. In the latch-up free load line case, the IV
characteristic of the snapback protection device intersects
the load-line in one unique point (VOP, IOP). This is the only
stable operating point of the circuit and the system is
therefore latch-up free. Please note that for USB 3.0
applications, ESD8006 latch-up free considerations are
explained in more detail in the above PCB layout guidelines.
In the non-latch up free load line case, the IV characteristic
of the snapback protection device intersects the load-line in
two points (VOPA, IOPA) and (VOPB, IOPB). Therefore in this
case, the potential for latch-up exists if the system settles at
(VOPB, IOPB) after a transient. Because of this, ESD8006
should not be used for HDMI applications – ESD8104 or
ESD8040 have been designed to be acceptable for HDMI
applications without latch-up. Please refer to Application
Note AND9116/D for a more in-depth explanation of
latch-up considerations using ESD8000 series devices.
II
ISSMAX
IOP
VOP VDD
V
ESD8006 Latch−up free:
USB 2.0 LS/FS, USB 2.0 HS, USB 3.0/3.1 SS,
DisplayPort
ISSMAX
IOPB
IOPA
VOPB
VOPA VDD V
ESD8006 Potential Latch−up:
HDMI 2.0/1.4/1.3a TMDS
Figure 20. Example Load Lines for Latch-up Free Applications and Applications with the Potential for Latch-up
Table 1. SUMMARY OF SCR REQUIREMENTS FOR LATCH-UP FREE APPLICATIONS
Application
VBR (min)
(V)
IH (min)
(mA)
VH (min)
(V)
ON Semiconductor ESD8000 Series
Recommended PN
HDMI 2.0/1.4/1.3a TMDS
3.465
54.78
1.0
ESD8104, ESD8040
USB 2.0 LS/FS
3.301
1.76
1.0
ESD8004
USB 2.0 HS
0.482
N/A
1.0
ESD8004
USB 3.0/3.1 SS
2.800
N/A
1.0
ESD8004, ESD8006
DisplayPort
3.600
25.00
1.0
ESD8004, ESD8006
www.onsemi.com
11
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| PDF Descargar | [ Datasheet SZESD8006MUTAG.PDF ] | |
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