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74VHC125 PDF 데이터시트 ( Data , Function )

부품번호 74VHC125 기능
기능 Quad buffer/line driver
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74VHC125 데이터시트, 핀배열, 회로
74VHC125; 74VHCT125
Quad buffer/line driver; 3-state
Rev. 02 — 13 October 2009
Product data sheet
1. General description
The 74VHC125; 74VHCT125 are high-speed Si-gate CMOS devices and are pin
compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with
JEDEC standard JESD7-A.
The 74VHC125; 74VHCT125 provides four non-inverting buffer/line drivers with 3-state
outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH
at nOE causes the outputs to assume a high-impedance OFF-state.
The 74VHC125; 74VHCT125 are identical to the 74VHC126; 74VHCT126 but have active
LOW enable inputs.
2. Features
I Balanced propagation delays
I All inputs have a Schmitt-trigger action
I Inputs accepts voltages higher than VCC
I Input levels:
N The 74VHC125 operates with CMOS logic levels
N The 74VHCT125 operates with TTL logic levels
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Multiple package options
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
Description
74VHC125D
74VHCT125D
40 °C to +125 °C SO14
plastic small outline package; 14 leads;
body width 3.9 mm
74VHC125PW 40 °C to +125 °C
74VHCT125PW
TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
74VHC125BQ 40 °C to +125 °C
74VHCT125BQ
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
Version
SOT108-1
SOT402-1
SOT762-1




74VHC125 pdf, 반도체, 판매, 대치품
NXP Semiconductors
74VHC125; 74VHCT125
Quad buffer/line driver; 3-state
8. Recommended operating conditions
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
VCC
VI
VO
Tamb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise
and fall rate
VCC = 3.3 V ± 0.3 V
VCC = 5.0 V ± 0.5 V
9. Static characteristics
74VHC125
Min Typ
2.0 5.0
0-
0-
40 +25
--
--
Max
5.5
5.5
VCC
+125
100
20
74VHCT125
Min Typ
4.5 5.0
0-
0-
40 +25
--
--
Max
5.5
5.5
VCC
+125
-
20
Unit
V
V
V
°C
ns/V
ns/V
Table 6. Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions
25 °C
40 °C to +85 °C 40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
For type 74VHC125
VIH HIGH-level VCC = 2.0 V
input voltage VCC = 3.0 V
1.5 - - 1.5
-
1.5
-V
2.1 - - 2.1
-
2.1
-V
VCC = 5.5 V
3.85 -
- 3.85
-
3.85
-V
VIL
LOW-level
VCC = 2.0 V
input voltage VCC = 3.0 V
- - 0.5 -
0.5
-
0.5 V
- - 0.9 -
0.9
-
0.9 V
VCC = 5.5 V
- - 1.65 -
1.65
-
1.65 V
VOH HIGH-level VI = VIH or VIL
output voltage IO = 50 µA; VCC = 2.0 V
1.9 2.0
-
1.9
-
1.9
-V
IO = 50 µA; VCC = 3.0 V 2.9 3.0 -
2.9
-
2.9
-V
IO = 50 µA; VCC = 4.5 V 4.4 4.5 -
4.4
-
4.4
-V
IO = 4.0 mA; VCC = 3.0 V 2.58 -
- 2.48
-
2.40
-V
IO = 8.0 mA; VCC = 4.5 V 3.94 - - 3.8 - 3.70 - V
VOL
LOW-level
VI = VIH or VIL
output voltage IO = 50 µA; VCC = 2.0 V
- 0 0.1 -
0.1
-
0.1 V
IO = 50 µA; VCC = 3.0 V
- 0 0.1 -
0.1
-
0.1 V
IO = 50 µA; VCC = 4.5 V
- 0 0.1 -
0.1
-
0.1 V
IO = 4.0 mA; VCC = 3.0 V - - 0.36 -
0.44
-
0.55 V
IO = 8.0 mA; VCC = 4.5 V - - 0.36 -
0.44
-
0.55 V
IOZ
OFF-state
VI = VIH or VIL;
output current VO = VCC or GND;
VCC = 5.5 V
- - ±0.25 - ±2.5 - ±10.0 µA
II input leakage VI = 5.5 V or GND;
current
VCC = 0 V to 5.5 V
- - 0.1 -
1.0
-
2.0 µA
ICC supply current VI = VCC or GND; IO = 0 A; - - 2.0 -
20
-
40 µA
VCC = 5.5 V
74VHC_VHCT125_2
Product data sheet
Rev. 02 — 13 October 2009
© NXP B.V. 2009. All rights reserved.
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74VHC125 전자부품, 판매, 대치품
NXP Semiconductors
74VHC125; 74VHCT125
Quad buffer/line driver; 3-state
Table 7. Dynamic characteristics …continued
GND = 0 V; For test circuit see Figure 8.
Symbol Parameter Conditions
For type 74VHCT125
tpd propagation nA to nY; see Figure 6
delay
VCC = 4.5 V to 5.5 V
CL = 15 pF
CL = 50 pF
ten enable time nOE to nY; see Figure 7
VCC = 4.5 V to 5.5 V
CL = 15 pF
CL = 50 pF
tdis disable time nOE to nY; see Figure 7
VCC = 4.5 V to 5.5 V
CL = 15 pF
CL = 50 pF
CPD power
CL = 50 pF; fi = 1 MHz;
dissipation VI = GND to VCC
capacitance
25 °C
40 °C to +85 °C 40 °C to +125 °C Unit
Min Typ[1] Max Min
Max
Min
Max
[2]
- 3.0 5.5 1.0
6.5
1.0
7.0 ns
- 4.3 7.5 1.0
8.5
1.0
9.5 ns
- 3.4 5.1 1.0
6.0
1.0
6.5 ns
- 4.9 7.3 1.0
8.3
1.0
9.5 ns
[2]
- 4.5 6.8 1.0
8.0
1.0
8.5 ns
- 6.5 8.8 1.0 10.0 1.0
11.0 ns
[3] -
12 -
-
-
-
- pF
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2] tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz, fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
Σ(CL × VCC2 × fo) = sum of the outputs.
11. Waveforms
nA input
VI
GND
VOH
nY output
VOL
VM
tPHL
VM
tPLH
mna230
Fig 6.
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Propagation delay input (nA) to output (nY)
74VHC_VHCT125_2
Product data sheet
Rev. 02 — 13 October 2009
© NXP B.V. 2009. All rights reserved.
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