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ISL6267 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 ISL6267
기능 Multiphase PWM Regulator
제조업체 Intersil Corporation
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ISL6267 데이터시트, 핀배열, 회로
Multiphase PWM Regulator for AMD Fusion™ Mobile
CPUs
ISL6267
The ISL6267 is designed to be completely compliant with AMD
Fusion™ specifications. The ISL6267 controls two Voltage
Regulators (VRs), with three integrated gate drivers. The first
VR can be configured as 3-, 2-, or 1-phase VR, while the second
output can be configured as 2- or 1-phase VR, providing
maximum flexibility. The two VRs share the serial control bus
to communicate with the CPU and achieve lower cost and
smaller board area compared with two-chip solutions.
The PWM modulator of the ISL6267 is based on Intersil’s R3
(Robust Ripple Regulator) Technology™. Compared with the
traditional multi-phase buck regulator, the R3 modulator
commands variable switching frequency during load
transients, achieving faster transient response. With the same
modulator, it naturally goes into pulse frequency modulation in
light load conditions, which achieves higher light load
efficiency and extends battery life.
The ISL6267 has several other key features. Both outputs
support DCR current sensing with a single NTC thermostat for
DCR temperature compensation or accurate resistor current
sensing. Both of the outputs utilize remote voltage sense,
adjustable switching frequency, current monitor, OC
protection, independent power-good indicators, temperature
monitors, and a common thermal alert.
Applications
• AMD fusion CPU/GPU core power
• Notebook computer
Features
• Supports AMD SVI 1.0 serial data bus interface
• Dual output controller with integrated drivers
- Core VR configurable 3-, 2-, 1-phase with two integrated
drivers
- Northbridge VR configurable 2- or 1-phase with one
integrated driver
• Precision voltage regulation
- 0.5% system accuracy over-temperature
- 0V to 1.55V in 12.5mV steps
- Enhanced load line accuracy
• Supports multiple current sensing methods
- Lossless inductor DCR current sensing
- Precision resistor current sensing
• Programmable 1-, 2- or 3-phase for the core output and 1- or
2-phase for the northbridge output
• Adaptive body diode conduction time reduction
• Superior noise immunity and transient response
• Output current monitor and thermal monitor
• Differential remote voltage sensing
• High efficiency across entire load range
• Programmable +VID offset for both core and NB
• Programmable switching frequency for both outputs
• Excellent dynamic current balance between phases
• OCP/WOC, OVP, PGOOD, and thermal monitor
• Small footprint 48 Ld 6x6 QFN package
• Pb-free (RoHS compliant)
Core Performance on ISL6267EVAL1Z
100
90
80
70
60
50
40
30
20
10
0
0
VIN = 12V
VIN = 19V
VIN = 8V
VOUT CORE = 1.1V
5 10 15 20 25 30 35 40 45 50 55
IOUT (A)
FIGURE 1. EFFICIENCY vs LOAD
1.12
1.10
1.08
1.06
1.04
1.02
VIN = 12V
VIN = 8V
1.00
VIN = 19V
0.98 VOUT CORE = 1.1V
0.96 0 5 10 15 20 25 30 35 40 45 50 55
IOUT (A)
FIGURE 2. VOUT vs LOAD
FN7801.1
January 8, 2013
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.




ISL6267 pdf, 반도체, 판매, 대치품
ISL6267
Simplified Application Circuit For Low Power CPU Core And NB
VNB1
+5V
OPEN
ISEN2_NB
ISEN1_NB
ISUMN_NB
ISUMP_NB
BOOT_NB
UG1_NB
PH1_NB
LG1_NB
VIN
NB_PH1
VNB
VNB1
optional
VW_NB
COMP_NB
NTC_NB
PWM2_NB
OPEN
VNB_SENSE
µP
OPEN
+5V
OPEN
optional
VCORE_SENSE
VO1
FB_NB
VSEN_NB
RTN_NB
PWROK
SVD
SVC
ISL6267
ISEN1
ISEN2
ISEN3
VW
COMP
FB
VSEN
RTN
ISUMN
PROG1
PROG2
NTC
VR_HOT
THERMAL INDICATOR
PWM3
BOOT2 OPEN
UG2
PH2
OPEN
OPEN
+5V
LG2 OPEN
PGND2
BOOT1
UG1
OPEN
PH1
LG1
VIN
PH1
ISUMP
VCORE
VO1
FIGURE 5. TYPICAL APPLICATION CIRCUIT USING INDUCTOR DCR SENSING
4
January 8, 2013
FN7801.1

4페이지










ISL6267 전자부품, 판매, 대치품
Pin Configuration
ISL6267
ISL6267
(48 LD QFN)
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37
FB2_NB 1
FB_NB 2
COMP_NB 3
VW_NB 4
PGOOD_NB 5
SVD 6
PWROK 7
SVC 8
ENABLE 9
PGOOD 10
VR_HOT 11
NTC 12
GND PAD
(BOTTOM)
36 PWM2_NB
35 BOOT2
34 UG2
33 PH2
32 LG2
31 VCCP
30 PWM3
29 LG1
28 PH1
27 UG1
26 BOOT1
25 PROG1
Pin Descriptions
PIN NUMBER
1
SYMBOL
FB2_NB
2 FB_NB
3 COMP_NB
4 VW_NB
5 PGOOD_NB
6 SVD
7 PWROK
8 SVC
9 ENABLE
10 PGOOD
11 VR_HOT
12 NTC
13 VW
14 COMP
15 FB
7
DESCRIPTION
The components connecting to FB2_NB are used to adjust the compensation in 1-phase mode to achieve
optimum performance.
Output voltage feedback to the inverting input of the Northbridge controller error amplifier.
Northbridge VR error amplifier output.
Window voltage set pin used to set the switching frequency for the Northbridge controller. A resistor from
this pin to COMP_NB programs the switching frequency (8kΩ gives approximately 300kHz).
Open-drain output to indicate the Northbridge portion of the IC is ready to supply regulated voltage.
Pull-up externally to VCCP or 3.3V.
Serial VID data bi-directional signal from the CPU processor master device to the VR.
System power good input. When this pin is high, the SVI interface is active and the I2C protocol is running.
While this pin is low, the SVC and SVD input states determine the pre-PWROK metal VID. This pin must
be low prior to the ISL6267 PGOOD output going high per the AMD SVI Controller Guidelines.
Serial VID clock input from the CPU processor master device.
Enable input. A high level logic on this pin enables both VRs.
Open-drain output to indicate the Core portion of the IC is ready to supply regulated voltage. Pull-up
externally to VCCP or 3.3V.
Thermal overload open drain output indicator active LOW.
Thermistor input to VR_HOT circuit to monitor Core VR temperature.
Window voltage set pin used to set the switching frequency for the Core controller. A resistor from this
pin to COMP programs the switching frequency (8kΩ gives approximately 300kHz).
Error amplifier output.
Output voltage feedback to the inverting input of the Core controller error amplifier.
January 8, 2013
FN7801.1

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