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73M1903 데이터시트 PDF




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부품번호 73M1903 기능
기능 Modem Analog Front End
제조업체 Teridian Semiconductor
로고 Teridian Semiconductor 로고


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73M1903 데이터시트, 핀배열, 회로
Simplifying System IntegrationTM
DESCRIPTION
The Teridian 73M1903 Analog Front End (AFE) IC
includes fully differential hybrid driver outputs, which
connect to the telephone line interface through a
transformer-based DAA. The receive pins are also
fully differential for maximum flexibility and
performance. This arrangement allows for the
design of a high performance hybrid circuit to
improve signal to noise performance under low
receive level conditions, and compatibility with any
standard transformer intended for PSTN
communications applications.
The device incorporates a programmable sample
rate circuit to support soft modem and DSP based
implementations of all speeds up to V.92 (56 kbps).
The sampling rates supported are from 7.2 kHz to
14.4 kHz by programming pre-scaler NCO and PLL
NCO.
The 73M1903 device incorporates a digital host
interface that is compatible with the serial ports
found on most commercially available DSPs and
processors and exchanges both payload and control
information with the host.
Cost-saving features of the device include an input
reference frequency circuit, which accepts a range
of crystals from 9-27 MHz. It also accepts external
reference clock values between 9-40 MHz
generated by the host processor. In most
applications, this eliminates the need for a dedicated
crystal oscillator and reduces the bill of material
(BOM).
The 73M1903 also supports two analog loop back
and one digital loop back test modes.
(HYBRID)
VBG
TXAP
TXAN
Transmit
Drivers/
Filters
Analog
Sigma
Delta
Ref.
SCLK
RXAP
RXAN
Receive
Mux/
Filters
Control Serial
DAC Registers Port
SDIN
SDOUT
FSB
GPIO
HOOK
DAA
Controls Clocks
Control
Logic
Crystal
73M1903
Modem Analog Front End
DATA SHEET
March 2010
FEATURES
Up to 56 kbps (V.92) performance
Programmable sample rates (7.2 - 14.4 kHz)
Reference clock range of 9-40 MHz
Crystal frequency range of 9-27 MHz
Host synchronous serial interface operation
Pin compatible with 73M2901CL/CE
modems
Low power modes
On board line interface drivers
Fully differential receiver and transmitter
Drivers for transformer interface
3.0 V – 3.6 V operation
5 V tolerant I/O
Industrial temperature range (-40 to +85 °C)
JATE compliant transmit spectrum
Package options:
32-pin QFN
20-pin TSSOP
RoHS compliant (6/6) lead-free packages
APPLICATIONS
Set Top Boxes
Personal Video Recorders (PVR)
Multifunction Peripherals (MFP)
Fax Machines
Internet Appliances
Game Consoles
Point of Sale Terminals
Automatic Teller Machines
Speaker Phones
RF Modems
Rev. 2.1
© 2010 Teridian Semiconductor Corporation
1




73M1903 pdf, 반도체, 판매, 대치품
73M1903 Data Sheet
DS_1903_032
1 Signal Description
The Teridian 73M1903 modem AFE IC is available in a 20-pin TSSOP or 32-pin QFN package with the
same pin out. The following table describes the function of each pin. There are two pairs of power
supply pins, VPA (analog) and VPD (digital). They should be decoupled separately from the supply
source in order to isolate digital noise from the analog circuits internal to the chip. Failure to adequately
isolate and decouple these supplies will compromise device performance.
Pin Name
VND
VNA
VPD
VPA
VPPLL
VNPLL
RST
OSCIN
OSCOUT
GPIO(0-7)
VREF
RXAP
RXAN
TXAP
TXAN
SCLK
SDOUT
SDIN
FS
TYPE
SckMode
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles
Type
GND
GND
PWR
PWR
PWR
PWR
I
I
O
I/O
O
I
I
O
O
O
32QFN
Pin #
1,22
16
2,25
10
20
17
9
19
18
3, 4, 5, 6,
23,
24,30,31
13
15
14
12
11
8
20VT
Pin#
2,18
13
3
8
17
14
7
16
15
N/A
6
12
11
10
9
5
Description
Negative Digital Ground
Negative Analog Ground
Positive Digital Supply
Positive Analog Supply
Positive PLL Supply, shared with VPD
Negative PLL Ground
Master reset. When this pin is a logic 0 all registers are
reset to their default states; Weak-pulled high- default.
Crystal oscillator input. When providing an external clock
source, drive OSCIN.
Crystal oscillator circuit output pin.
Software definable digital input/output pins. Not available in
the 20VT (TSSOP) package.
Reference voltage pin (Reflects VREF).
Receive analog positive input.
Receive analog negative input.
Transmit analog positive output.
Transmit analog negative output.
Serial interface clock. With SCLK continuous selected,
Frequency = 256*Fs ( =2.4576 MHz for Fs=9.6 kHz)
O 32 1 Serial data output (or input to the host).
I 29 20 Serial data input (or output from the host).
O 7 4 Frame synchronization. (Active Low)
I
27
19 Type of frame sync. Open, weak-pulled high = early
(mode1); tied low = late (mode0).
Controls the SCLK behavior after FS. Open, weak-pulled
I 28 NA high = SCLK Continuous; tied low = 32 clocks per R/W
cycle. Not available in 20VT.
4 Rev. 2.1

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73M1903 전자부품, 판매, 대치품
DS_1903_032
73M1903 Data Sheet
SCLK
FS(mode1)
SCLK
FS(mode0)
32 Cycles of sclk
32 Cycles of sclk
SCLK and FS in mode 1
SCLK and FS in mode 0
Figure 1: Effect of the TYPE (FS mode) pin on FS with SckMode = 0
Figure 2: Control Frame Position versus SPOS
Rev. 2.1
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