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부품번호 Am5X86
기능 Microprocessor
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Am5X86 데이터시트, 핀배열, 회로
PRELIMINARY
Am5X86
Microprocessor Family
Advanced
Micro
Devices
DISTINCTIVE CHARACTERISTICS
s High-Performance Design
Industry-standard write-back cache support
Frequent instructions execute in one clock
105.6-million bytes/second burst bus at 33 MHz
Flexible write-through and write-back address
control
Advanced 0.35-µ CMOS-process technology
Dynamic bus sizing for 8-, 16-, and 32-bit buses
— Supports “soft reset” capability
s High On-Chip Integration
16-Kbyte unified code and data cache
— Floating-point unit
— Paged, virtual memory management
s Enhanced System and Power Management
Stop clock control for reduced power
consumption
Industry-standard two-pin System Management
Interrupt (SMI) for power management indepen-
dent of processor operating mode and operating
system
— Static design with Auto Halt power-down support
— Wide range of chipsets supporting SMM avail-
able to allow product differentiation
s Complete 32-Bit Architecture
Address and data buses
All registers
— 8-, 16-, and 32-bit data types
s Standard Features
3-V core with 5-V tolerant I/O
Available in a 133-MHz version
Binary compatible with all Am486®DX,
Am486DX2, and Am486DX4 microprocessors
Wide range of chipsets and support available
through the AMD FusionPCSM Program
s 168-pin PGA package or 208-pin SQFP package
s IEEE 1149.1 JTAG Boundary-Scan Compatibility
s Supports Environmental Protection Agency's
Energy Star program
— 3-V operation reduces power consumption up to
40%
Energy management capability provides excel-
lent base for energy-efficient design
— Works with a variety of energy-efficient, power-
managed devices
GENERAL DESCRIPTION
The Am5X86™ microprocessor is an addition to the AMD
microprocessor product family. The new processor en-
hances system performance by raising the microproces-
sor operating frequency to the highest levels allowed by
current manufacturing technology, while maintaining
complete compatibility with the standard Am486 proces-
sor architecture and Microsoft® Windows®. The CPUs
incorporate write-back cache, flexible clock control, and
enhanced SMM. Table 1 shows available processors
in the Am5X86 microprocessor family.
Table 1. Clocking Options
Operating
Frequency
133 MHz
133 MHz
Input Clock
33 MHz
33 MHz
Available Package
168-pin PGA
208-pin SQFP
The Am5X86 microprocessor family allows write-back
configuration through software and cacheable access
control. On-chip cache lines are configurable as either
write-through or write-back. The CPU clock control fea-
ture permits the CPU clock to be stopped under con-
trolled conditions, allowing reduced power consumption
during system inactivity. The SMM function is implement-
ed with an industry standard two-pin interface.
This document contains information on a product under development at Advanced Micro Devices. The information is
intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication # 19751 Rev: C Amendment/0
Issue Date: March 1996




Am5X86 pdf, 반도체, 판매, 대치품
AMD
PRELIMINARY
Table of Contents
1 Connection Diagrams and Pin Designations ......................................................................................... 8
1.1 168-Pin PGA (Pin Grid Array) Package .......................................................................................... 8
1.2 168-Pin PGA Designations (Functional Grouping) ......................................................................... 9
1.3 208-Pin SQFP (Shrink Quad Flat Pack) Package ........................................................................ 10
1.4 208-Pin SQFP Designations (Functional Grouping) ..................................................................... 11
2 Logic Symbol ...................................................................................................................................... 12
3 Pin Description .................................................................................................................................... 13
4 Functional Description ........................................................................................................................ 18
4.1 Overview ....................................................................................................................................... 18
4.2 Memory ......................................................................................................................................... 18
4.3 Modes of Operation ...................................................................................................................... 18
4.3.1 Real mode ........................................................................................................................... 18
4.3.2 Virtual mode ........................................................................................................................ 18
4.3.3 Protected mode ................................................................................................................... 18
4.3.4 System Management mode ................................................................................................ 18
4.4 Cache Architecture ....................................................................................................................... 18
4.4.1 Write-Through Cache .......................................................................................................... 18
4.4.2 Write-Back Cache ............................................................................................................... 18
4.5 Write-Back Cache Protocol ........................................................................................................... 19
4.5.1 Cache Line Overview .......................................................................................................... 19
4.5.2 Line Status and Line State .................................................................................................. 19
4.5.2.1 Invalid ......................................................................................................................... 19
4.5.2.2 Exclusive .................................................................................................................... 19
4.5.2.3 Shared ....................................................................................................................... 19
4.5.2.4 Modified ..................................................................................................................... 19
4.6 Cache Replacement Description .................................................................................................. 20
4.7 Memory Configuration ................................................................................................................... 20
4.7.1 Cacheability ......................................................................................................................... 20
4.7.2 Write-Through/Write-Back ................................................................................................... 20
4.8 Cache Functionality in Write-Back mode ...................................................................................... 20
4.8.1 Processor-Initiated Cache Functions and State Transitions ............................................... 20
4.8.2 Snooping Actions and State Transitions ............................................................................. 21
4.8.2.1 Difference between Snooping Access Cases ............................................................ 21
4.8.2.2 HOLD Bus Arbitration Implementation ....................................................................... 22
4.8.2.2.1 Processor-Induced Bus Cycles ........................................................................ 22
4.8.2.2.2 External Read ................................................................................................... 22
4.8.2.2.3 External Write ................................................................................................... 22
4.8.2.2.4 HOLD/HLDA External Access TIming .............................................................. 22
4.8.3 External Bus Master Snooping Actions ............................................................................... 25
4.8.3.1 Snoop Miss ................................................................................................................. 25
4.8.3.2 Snoop Hit to a Non-Modified Line .............................................................................. 25
4.8.4 Write-Back Case ................................................................................................................. 25
4.8.5 Write-Back and Pending Access ......................................................................................... 26
4.8.5.1 HOLD/HLDA Write-Back Design Considerations ....................................................... 27
4.8.5.2 AHOLD Bus Arbitration Implementation .................................................................... 28
4.8.5.3 Normal Write-Back ..................................................................................................... 28
4.8.6 Reordering of Write-Backs (AHOLD) with BOFF ................................................................. 29
4.8.7 Special Scenarios For AHOLD Snooping ............................................................................ 30
4.8.7.1 Write Cycle Reordering due to Buffering ................................................................... 30
4.8.7.2 BOFF Write-Back Arbitration Implementation ............................................................ 32
4.8.8 BOFF Design Considerations .............................................................................................. 32
4.8.8.1 Cache Line Fills ......................................................................................................... 32
4.8.8.2 Cache Line Copy-Backs ............................................................................................ 32
4.8.8.3 Locked Accesses ....................................................................................................... 32
4 Am5X86 Microprocessor

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Am5X86 전자부품, 판매, 대치품
PRELIMINARY
AMD
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Figure 40
Figure 41
Figure 42
Figure 43
Figure 44
Figure 45
Figure 46
SMM Base Slot Offset ............................................................................................................. 48
SRAM Usage .......................................................................................................................... 48
SMRAM Location .................................................................................................................... 49
SMM Timing in Systems Using Non-Overlaid Memory Space and Write-Through Mode
with Caching Enabled During SMM.......................................................................................... 50
SMM Timing in Systems Using Non-Overlaid Memory Spaces and Write-Back Mode with
Caching Enabled During SMM ................................................................................................. 50
SMM Timing in Systems Using Non-Overlaid Memory Spaces and Write-Back Mode with
Caching Disabled During SMM ................................................................................................ 50
SMM Timing in Systems Using Overlaid Memory Space and Write-Through Mode with
Caching Enabled During SMM ................................................................................................. 51
SMM Timing in Systems Using Overlaid Memory Spaces and Write-Through Mode with
Caching Disabled During SMM ................................................................................................ 51
SMM Timing in Systems Using Overlaid Memory Spaces and Configured in
Write-Back Mode...................................................................................................................... 51
CLK Waveforms ...................................................................................................................... 61
Output Valid Delay Timing ...................................................................................................... 61
Maximum Float Delay Timing .................................................................................................. 62
PCHK Valid Delay Timing ....................................................................................................... 62
Input Setup and Hold Timing ................................................................................................... 63
RDY and BRDY Input Setup and Hold Timing ........................................................................ 63
TCK Waveforms ...................................................................................................................... 64
Test Signal Timing Diagram .................................................................................................... 64
LIST OF TABLES
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Clocking Options ....................................................................................................................... 1
EADS Sample Time ................................................................................................................ 14
Cache Line Organization ......................................................................................................... 19
Legal Cache Line States ......................................................................................................... 19
MESI Cache Line Status ......................................................................................................... 20
Key to Switching Waveforms ................................................................................................... 22
WBINVD/INVD Special Bus Cycles ......................................................................................... 33
FLUSH Special Bus Cycles ..................................................................................................... 34
Pin State during Stop Grant Bus State .................................................................................... 37
SMRAM State Save Map ........................................................................................................ 43
SMM Initial CPU Core Register Settings ................................................................................. 45
Segment Register Initial States ............................................................................................... 45
SMM Revision Identifier .......................................................................................................... 46
SMM Revision Identifier Bit Definitions ................................................................................... 46
HALT Auto Restart Configuration ............................................................................................ 47
I/O Trap Word Configuration ................................................................................................... 47
Test Register TR4 Bit Descriptions ......................................................................................... 53
Test Register TR5 Bit Descriptions ......................................................................................... 53
CPU ID Codes ......................................................................................................................... 56
CPUID Instruction Description ................................................................................................. 56
Thermal Resistance (°C/W) θJC and θJA for the Am5X86 CPU in 168-Pin PGA Package ....... 65
Maximum TA at Various Airflows in °C .................................................................................... 65
Maximum TA for SQFP Package by Clock Frequency ............................................................. 65
Am5X86 Microprocessor
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