PDF Am5X86 Data sheet ( Hoja de datos )

Número de pieza	Am5X86
Descripción	Microprocessor
Fabricantes	AMD
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PRELIMINARY Am5X86™ Microprocessor Family Advanced Micro Devices DISTINCTIVE CHARACTERISTICS s High-Performance Design — Industry-standard write-back cache support — Frequent instructions execute in one clock — 105.6-million bytes/second burst bus at 33 MHz — Flexible write-through and write-back address control — Advanced 0.35-µ CMOS-process technology — Dynamic bus sizing for 8-, 16-, and 32-bit buses — Supports “soft reset” capability s High On-Chip Integration — 16-Kbyte unified code and data cache — Floating-point unit — Paged, virtual memory management s Enhanced System and Power Management — Stop clock control for reduced power consumption — Industry-standard two-pin System Management Interrupt (SMI) for power management indepen- dent of processor operating mode and operating system — Static design with Auto Halt power-down support — Wide range of chipsets supporting SMM avail- able to allow product differentiation s Complete 32-Bit Architecture — Address and data buses — All registers — 8-, 16-, and 32-bit data types s Standard Features — 3-V core with 5-V tolerant I/O — Available in a 133-MHz version — Binary compatible with all Am486®DX, Am486DX2, and Am486DX4 microprocessors — Wide range of chipsets and support available through the AMD FusionPCSM Program s 168-pin PGA package or 208-pin SQFP package s IEEE 1149.1 JTAG Boundary-Scan Compatibility s Supports Environmental Protection Agency's Energy Star program — 3-V operation reduces power consumption up to 40% — Energy management capability provides excel- lent base for energy-efficient design — Works with a variety of energy-efficient, power- managed devices GENERAL DESCRIPTION The Am5X86™ microprocessor is an addition to the AMD microprocessor product family. The new processor en- hances system performance by raising the microproces- sor operating frequency to the highest levels allowed by current manufacturing technology, while maintaining complete compatibility with the standard Am486 proces- sor architecture and Microsoft® Windows®. The CPUs incorporate write-back cache, flexible clock control, and enhanced SMM. Table 1 shows available processors in the Am5X86 microprocessor family. Table 1. Clocking Options Operating Frequency 133 MHz 133 MHz Input Clock 33 MHz 33 MHz Available Package 168-pin PGA 208-pin SQFP The Am5X86 microprocessor family allows write-back configuration through software and cacheable access control. On-chip cache lines are configurable as either write-through or write-back. The CPU clock control fea- ture permits the CPU clock to be stopped under con- trolled conditions, allowing reduced power consumption during system inactivity. The SMM function is implement- ed with an industry standard two-pin interface. This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication # 19751 Rev: C Amendment/0 Issue Date: March 1996 1 page PRELIMINARY AMD 4.8.9 BOFF During Write-Back ..................................................................................................... 32 4.8.10 Snooping Characteristics During a Cache Line Fill ........................................................... 32 4.8.11 Snooping Characteristics During a Copy-Back ................................................................. 32 4.9 Cache Invalidation and Flushing in Write-Back mode .................................................................. 33 4.9.1 Cache Invalidation through Software .................................................................................. 33 4.9.2 Cache Invalidation through Hardware ................................................................................. 33 4.9.3 Snooping During Cache Flushing ........................................................................................ 34 4.10 Burst Write .................................................................................................................................. 34 4.10.1 Locked Accesses .............................................................................................................. 35 4.10.2 Serialization ....................................................................................................................... 35 4.10.3 PLOCK Operation in Write-Through mode ........................................................................ 36 5 Clock Control ...................................................................................................................................... 36 5.1 Clock Generation .......................................................................................................................... 36 5.2 Stop Clock ..................................................................................................................................... 36 5.2.1 External Interrupts in Order of Priority ................................................................................. 36 5.3 Stop Grant Bus Cycle ................................................................................................................... 36 5.4 Pin State during Stop Grant .......................................................................................................... 37 5.5 Clock Control State Diagram ........................................................................................................ 37 5.5.1 Normal State ........................................................................................................................ 37 5.5.2 Stop Grant State .................................................................................................................. 37 5.5.3 Stop Clock State .................................................................................................................. 39 5.5.4 Auto Halt Power Down State ............................................................................................... 39 5.5.5 Stop Clock Snoop State (Cache Invalidations) .................................................................... 39 5.5.6 Cache Flush State ............................................................................................................... 39 6 SRESET Function ............................................................................................................................... 39 7 System Management mode ................................................................................................................ 39 7.1 Overview ....................................................................................................................................... 39 7.2 Terminology .................................................................................................................................. 40 7.3 System Management Interrupt Processing ................................................................................... 40 7.3.1 System Management Interrupt Processing ......................................................................... 41 7.3.2 SMI Active (SMIACT) .......................................................................................................... 41 7.3.3 SMRAM ............................................................................................................................... 42 7.3.4 SMRAM State Save Map .................................................................................................... 43 7.4 Entering System Management mode ............................................................................................ 44 7.5 Exiting System Management mode .............................................................................................. 44 7.6 Processor Environment ................................................................................................................. 44 7.7 Executing System Management mode Handler ............................................................................ 45 7.7.1 Exceptions and Interrupts with System Management mode ............................................... 46 7.7.2 SMM Revisions Identifier ..................................................................................................... 46 7.7.3 Auto HALT Restart .............................................................................................................. 47 7.7.4 I/O Trap Restart ................................................................................................................... 47 7.7.5 I/O Trap Word ...................................................................................................................... 47 7.7.6 SMM Base Relocation ......................................................................................................... 48 7.8 SMM System Design Considerations ........................................................................................... 48 7.8.1 SMRAM Interface ................................................................................................................ 48 7.8.2 Cache Flushes .................................................................................................................... 49 7.8.3 A20M Pin ............................................................................................................................. 49 7.8.4 CPU Reset during SMM ...................................................................................................... 52 7.8.5 SMM and Second Level Write Buffers ................................................................................ 52 7.8.6 Nested SMI and I/O Restart ................................................................................................ 52 7.9 SMM Software Considerations ..................................................................................................... 52 7.9.1 SMM Code Considerations ................................................................................................. 52 7.9.2 Exception Handling ............................................................................................................. 52 7.9.3 Halt during SMM .................................................................................................................. 53 7.9.4 Relocating SMRAM to an Address above 1 Mbyte ............................................................. 53 Am5X86 Microprocessor 5 5 Page PRELIMINARY 1.4 208-pin SQFP Designations (Functional Grouping) Address Pin Name A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pin No. 202 197 196 195 193 192 190 187 186 182 180 178 177 174 173 171 166 165 164 161 160 159 158 154 153 152 151 149 148 147 Data Pin Name D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 Pin No. 144 143 142 141 140 130 129 126 124 123 119 118 117 116 113 112 108 103 101 100 99 93 92 91 87 85 84 83 79 78 75 74 Control Pin Name A20M ADS AHOLD BE0 BE1 BE2 BE3 BLAST BOFF BRDY BREQ BS8 BS16 CACHE CLK CLKMUL D/C DP0 DP1 DP2 DP3 EADS FERR FLUSH HITM HLDA HOLD IGNNE INTR INV KEN LOCK M/IO NMI PCD PCHK PLOCK PWT RDY RESET SMI SRESET STPCLK SMIACT UP WB/WT W/R Pin No. 47 203 17 31 32 33 34 204 6 5 30 8 7 70 24 11 39 145 125 109 90 46 66 49 63 26 16 72 50 71 13 207 37 51 41 4 206 40 12 48 65 58 73 59 194 64 27 Test Pin Name TCK TDI TDO TMS Pin No. 18 168 68 167 Note: INC = Internal No Connect AMD INC Vcc Vss Pin Pin Pin No. No. No. 3 21 67 9 10 96 14 15 127 19 21 20 28 22 36 23 43 25 52 29 53 35 55 38 57 42 61 44 76 45 81 54 88 56 94 60 97 62 104 69 105 77 107 80 110 82 115 86 120 89 122 95 132 98 135 102 138 106 146 111 156 114 157 121 170 128 175 131 181 133 184 134 189 136 199 137 201 139 208 150 155 162 163 169 172 176 179 183 185 188 191 198 200 205 Am5X86 Microprocessor 11 11 Page

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