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PDF IS61WV25616EDBLL Data sheet ( Hoja de datos )
| Número de pieza | IS61WV25616EDBLL | |
| Descripción | 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM | |
| Fabricantes | ISSI | |
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IS61WV25616EDBLL
IS64WV25616EDBLL
256K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH ECC
OCTOBER 2011
FEATURES
• High-speed access time: 8, 10 ns
• Low Active Power: 85 mW (typical)
• Low Standby Power: 7 mW (typical)
CMOS standby
• Single power supply
— Vdd 2.4V to 3.6V (10 ns)
— Vdd 3.3V ± 10% (8 ns)
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial and Automotive temperature support
• Lead-free available
• Error Detection and Error Correction
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
The ISSI IS61/64WV25616EDBLL is a high-speed,
4,194,304-bit static RAMs organized as 262,144 words
by 16 bits. It is fabricated using ISSI's high-performance
CMOS technology. This highly reliable process coupled
with innovative circuit design techniques, yields high-
performance and low power consumption devices.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be re-
duced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS61/64WV25616EDBLL is packaged in the JEDEC
standard 44-pin TSOP-II and 48-pin Mini BGA (6mm x
8mm).
A0-A17
Decoder
Memory
Lower IO
Array-
256Kx8
ECC
Array-
256K
x4
Memory
Upper IO
Array-
256Kx8
ECC
Array-
256K
x4
IO0-7
IO8-15
8 8 12 8
8
I/O Data
Circuit
8
ECC
12
ECC
48
Column I/O
4
/CE
/OE Control
/WE
/UB
Circuit
/LB
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
09/29/2011
1
1 page  
IS61/64WV25616EDBLL
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 3.3V + 10%
Symbol Parameter
Test Conditions
Min.
Voh
Output HIGH Voltage
Vdd = Min., Ioh = –4.0 mA
2.4
Vol
Output LOW Voltage
Vdd = Min., Iol = 8.0 mA
—
Vih
Input HIGH Voltage
2
Vil
Input LOW Voltage(1)
–0.3
Ili
Input Leakage
GND ≤ Vin ≤ Vdd
–1
Ilo
Output Leakage
GND ≤ Vout ≤ Vdd, Outputs Disabled
–1
Note:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested.
Max.
—
0.4
Vdd + 0.3
0.8
1
1
Unit
V
V
V
V
µA
µA
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 2.4V-3.6V
Symbol Parameter
Test Conditions
Min.
Voh
Output HIGH Voltage
Vdd = Min., Ioh = –1.0 mA
1.8
Vol
Output LOW Voltage
Vdd = Min., Iol = 1.0 mA
—
Vih
Input HIGH Voltage
2.0
Vil
Input LOW Voltage(1)
–0.3
Ili
Input Leakage
GND ≤ Vin ≤ Vdd
–1
Ilo
Output Leakage
GND ≤ Vout ≤ Vdd, Outputs Disabled
–1
Note:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested.
Max.
—
0.4
Vdd + 0.3
0.8
1
1
Unit
V
V
V
V
µA
µA
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 -10 -20
Symbol Parameter
Test Conditions Min. Max. Min. Max. Min. Max.
Icc Vdd Dynamic Operating Vdd = Max.,
Com. — 40
— 30
— 25
Supply Current
Iout = 0 mA, f = fmax Ind. — 45
— 35
— 30
Auto. — —
— 50
— 45
typ.(2) 21
21
Icc1
Operating
Supply Current
Vdd = Max.,
Iout = 0 mA, f = 0
Com. — 20
Ind. — 25
Auto. — —
— 20
— 25
— 40
— 20
— 25
— 40
Isb1 TTL Standby Current
(TTL Inputs)
Vdd = Max.,
Vin = Vih or Vil
CE ≥ Vih, f = 0
Com. — 10
Ind. — 15
Auto. — —
— 10
— 15
— 30
— 10
— 15
— 30
Isb2
CMOS Standby
Current (CMOS Inputs)
Vdd = Max.,
CE ≥ Vdd – 0.2V,
Vin ≥ Vdd – 0.2V, or
Vin ≤ 0.2V, f = 0
Com. — 5
Ind. — 6
Auto. — —
typ.(2) 1.5
— 5
— 6
— 15
1.5
— 5
— 6
— 15
Unit
mA
mA
mA
mA
Note:
1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested.
1
2
3
4
5
6
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
09/29/2011
5
5 Page 
IS61/64WV25616EDBLL
HIGH SPEED (IS61/64WV25616EDBLL)
DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V)
Symbol Parameter
Test Condition
Vdr
Vdd for Data Retention
See Data Retention Waveform
Idr
Data Retention Current Vdd = 2.0V, CE ≥ Vdd – 0.2V
tsdr
Data Retention Setup Time See Data Retention Waveform
trdr
Recovery Time
See Data Retention Waveform
Note 1: Typical values are measured at Vdd = Vdr(min), Ta = 25oC and not 100% tested.
Options
Com.
Ind.
Auto.
Min.
2.0
—
—
0
trc
Typ.(1)
—
0.5
—
—
—
Max.
3.6
5
6
15
—
—
Unit
V
mA
ns
ns
DATA RETENTION WAVEFORM (CE Controlled)
tSDR
Data Retention Mode
tRDR
VDD
1
2
3
4
5
6
VDR
CE
GND
CE ≥ VDD - 0.2V
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
09/29/2011
11
11 Page | ||
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