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PDF 74VHC126 Data sheet ( Hoja de datos )

Número de pieza 74VHC126
Descripción Quad buffer/line driver
Fabricantes NXP Semiconductors 
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No Preview Available ! 74VHC126 Hoja de datos, Descripción, Manual

74VHC126; 74VHCT126
Quad buffer/line driver; 3-state
Rev. 01 — 13 August 2009
Product data sheet
1. General description
The 74VHC126; 74VHCT126 are high-speed Si-gate CMOS devices and are pin
compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with
JEDEC standard No. 7-A.
The 74VHC126; 74VHCT126 provide four non-inverting buffer/line drivers with 3-state
outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE).
A LOW-level at pin nOE causes the outputs to assume a high-impedance OFF-state.
The 74VHC126; 74VHCT126 are identical to the 74VHC125; 74VHCT125 but have active
HIGH output enable inputs.
2. Features
I Balanced propagation delays
I All inputs have Schmitt-trigger action
I Inputs accept voltages higher than VCC
I Input levels:
N The 74VHC126 operates with CMOS input level
N The 74VHCT126 operates with TTL input level
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Multiple package options
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C

1 page




74VHC126 pdf
NXP Semiconductors
74VHC126; 74VHCT126
Quad buffer/line driver; 3-state
8. Recommended operating conditions
Table 5. Operating conditions
Symbol
Parameter
74VHC126
VCC
VI
VO
Tamb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
74VHCT126
VCC
VI
VO
Tamb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
Conditions
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
9. Static characteristics
Min Typ Max Unit
2.0 5.0 5.5 V
0-
5.5 V
0-
VCC
V
40 +25 +125 °C
- - 100 ns/V
- - 20 ns/V
4.5 5.0 5.5 V
0-
5.5 V
0-
VCC
V
40 +25 +125 °C
- - 20 ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions
25 °C
40 °C to +85 °C 40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
74VHC126
VIH HIGH-level VCC = 2.0 V
input voltage VCC = 3.0 V
1.5 - - 1.5
-
1.5
-V
2.1 - - 2.1
-
2.1
-V
VCC = 5.5 V
3.85 -
- 3.85
-
3.85
-V
VIL
LOW-level
VCC = 2.0 V
input voltage VCC = 3.0 V
- - 0.5 -
0.5
-
0.5 V
- - 0.9 -
0.9
-
0.9 V
VCC = 5.5 V
- - 1.65 -
1.65
-
1.65 V
VOH HIGH-level VI = VIH or VIL
output voltage IO = 50 µA; VCC = 2.0 V
1.9 2.0
-
1.9
-
1.9
-V
IO = 50 µA; VCC = 3.0 V 2.9 3.0 -
2.9
-
2.9
-V
IO = 50 µA; VCC = 4.5 V 4.4 4.5 -
4.4
-
4.4
-V
IO = 4.0 mA; VCC = 3.0 V 2.58 -
- 2.48
-
2.40
-V
IO = 8.0 mA; VCC = 4.5 V 3.94 -
- 3.80
-
3.70
-V
VOL
LOW-level
VI = VIH or VIL
output voltage IO = 50 µA; VCC = 2.0 V
- 0 0.1 -
0.1
-
0.1 V
IO = 50 µA; VCC = 3.0 V
- 0 0.1 -
0.1
-
0.1 V
IO = 50 µA; VCC = 4.5 V
- 0 0.1 -
0.1
-
0.1 V
IO = 4.0 mA; VCC = 3.0 V - - 0.36 -
0.44
-
0.55 V
IO = 8.0 mA; VCC = 4.5 V - - 0.36 -
0.44
-
0.55 V
74VHC_VHCT126_1
Product data sheet
Rev. 01 — 13 August 2009
© NXP B.V. 2009. All rights reserved.
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5 Page





74VHC126 arduino
NXP Semiconductors
74VHC126; 74VHCT126
Quad buffer/line driver; 3-state
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
y
Z
14
8
c
EA
X
HE v M A
pin 1 index
1
e
7
bp
wM
A2
A1
Q
(A3)
A
Lp
L
detail X
θ
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
D (1) E (2)
e
5.1
4.9
4.5
4.3
0.65
HE
6.6
6.2
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
JEITA
SOT402-1
MO-153
L Lp Q v w y Z (1) θ
1
0.75 0.4
0.50 0.3
0.2 0.13 0.1
0.72
0.38
8o
0o
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Fig 10. Package outline SOT402-1 (TSSOP14)
74VHC_VHCT126_1
Product data sheet
Rev. 01 — 13 August 2009
© NXP B.V. 2009. All rights reserved.
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