CH7512B Datasheet PDF - Chrontel
| Part Number | CH7512B | |
| Description | DP to LVDS Monitor Controller | |
| Manufacturers | Chrontel | |
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Chrontel
CH7512B
Brief Datasheet
CH7512B DP to LVDS Monitor Controller
FEATURES
• Supports DisplayPort Specification version 1.1a
• Support 2 Main Link Lanes at either 1.62Gb/s or
2.7Gb/s link rate for notebook PC applications
• Supports input color depth 6, 8-bit per pixel in RGB
format
• Supports Enhanced Framing Mode
• Support VESA and CEA timing standards up to
1920x1200 resolution in 8-bit input with 60Hz refresh
rate
• HDCP engine compliant with HDCP 1.3 specification
with internal HDCP Keys
• Support dynamic refresh rate switching
• Support Gamma correction
• Panel tuning methods including dithering and 6-bit +
FRC
• Fast and full Link Training for DisplayPort system
• 2 work modes: connect 27MHz crystal, inject 27MHz
clock
• Programmable LCD panel power sequence
• Support 18-bit Single Port, 18-bit Dual Port, 24-bit
Single Port and 24-bit Dual Port LVDS output interface
• Support both OpenLDI and SPWG bit mapping for
LVDS application
• Support panel select by GPIO pins control or writing
the chip registers.
• Flexible LVDS output pins swapping
• Blank panel during invalid input
• Supports PWM. Backlight luminance level control
through AUX channel, PWM pin and BLUP/BLDN pin
Support Dynamic Backlight Control
• Support OSD display when BLUP/BLDN pins control
Backlight Luminance
• Hot Plug Detection
• Loads Boot ROM automatically upon power up
• Serial BOOT ROM data updated through I2C bus or
AUX Channel
• Programmable power management
• EMI reduction capability for DP input and LVDS
output. Spread spectrum control is available for
transmitting LVDS signal
• Offered in a 68-pin QFN package
GENERAL DESCRIPTION
Chrontel’s CH7512B is a low-cost, low-power semiconductor
device that translates the DisplayPort signal to the LVDS (Low-
voltage Differential Signaling). This innovative DisplayPort
receiver with an integrated LVDS transmitter is specially
designed to target the All-In-One PC and the notebook market
segments. Through the CH7512B’s advanced decoding /
encoding algorithm, the input DisplayPort high-speed serialized
video data can be seamlessly converted to LVDS, a popular
display technology for high-speed serial links in mid/large-sized
LCD displays. Leveraging the DisplayPort’s unique source/sink
“Link Training” routine, the CH7512B is capable of instantly
bring up the video display to the LCD when the initialization
process is completed between CH7512B and the graphic chip.
The CH7512B is designed to meet the DisplayPort Specification
1.1a. In the device’s receiver block, which supports two
DisplayPort Main Link Lanes input with data rate running at
either 1.62Gb/s or 2.7Gb/s, can accept RGB digital formats in
either 18-bit 6:6:6 or 24-bit 8:8:8 for LVDS output up to
1920x1200. To comply with GPU’s new power saving scheme
such as display frame rate reduction, the CH7512B is equipped
with the Dynamic Refresh Rate switching method, which can
automatically reduce to the low refresh rate supported by the
LVDS panel.
The integrated LVDS transmitter supports the single port and
the dual ports LVDS outputs to drive display resolution up to
WUXGA (1920x1200). CH7512B supports panel select by
GPIO[0:3] pins control or writing the chip registers. To reduce
EMI emission, the CH7512B’s LVDS encoder block has
incorporated Spread Spectrum control and its spread percentage
can be adjusted through the internal registers.
The Backlight On/Off and the PWM are two luminance control
functions designed in the CH7512B LVDS power control
module. The brightness control commands sent through AUX
Channel can be dynamically translated by CH7512B and
converted into LCD backlight control signal. The CH7512B will
save the last setting of brightness level into the BOOT ROM and
restore it upon power up. The CH7512B can dynamically adjust
backlight brigntness according to video stream to save power
consumption and it supports OSD display in this way.
The CH7512B will immediately convert the DisplayPort signal
to LVDS output after DisplayPort Link Training is completed.
This feature can be achieved by loading the panel’s EDID and
the CH7512B’s configuration settings in the serial BOOT ROM
connected to the CH7512B. During system power-up and upon
completion of the DisplayPort Link Training through AUX
Channel, CH7512B will generate LVDS signal according to the
panel power-up timing sequencing stored in the BOOT ROM.
209-1000-041 Rev. 1.12 07/18/2013
1
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CHRONTEL
Pin #
58
Type Symbol
Out OLED
59 Out HPDET
61,62
64,65
In DP[1:0]P/N
68 In RBIAS
3,4,60,66,6 Power AVDD
7
7,42 Power DVDD
18,32,52 Power LVDD
8,21,35,40,
45,63,
Thermal
Exposed
Pad
Power
GND
CH7512B
Description
Orange LED Control
This pin indicates CH7512B in abnormal power and mode status. Its output
flickers from 0 or 3.3V.
Hot Plug Detect
This output pin is used as the connection detection by a DisplayPort Source
system. It generates interrupt pulse as defined by DisplayPort standard. The
output voltage is 3.3V. A 100 kΩ resistor should be connected between this
pin and GND. It should be linked to DisplayPort source.
Main Link Lane Input
These pins accept two AC-coupled differential pairs signals from the
DisplayPort transmitter.
Band-gap Bias input
A 10 KΩ(1%) resistor should be connected between this pin and GND.
Analog Power Supply (1.8V)
Digital Power Supply (1.8V)
LVDS Driver Power Supply and GPO Power Supply (3.3V)
Power Ground
209-1000-041 Rev. 1.12 07/18/2013
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for CH7512B electronic component. |
| Information | Total 7 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ CH7512B.PDF Datasheet ] | |
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