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A4986 PDF 데이터시트 ( Data , Function )

부품번호 A4986 기능
기능 DMOS Dual Full-Bridge PWM Motor Driver
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A4986 데이터시트, 핀배열, 회로
A4986
DMOS Dual Full-Bridge PWM Motor Driver
with Overcurrent Protection
Features and Benefits
Low RDS(ON) outputs
Internal mixed current decay mode
Synchronous rectification for low power dissipation
Internal UVLO
Crossover-current protection
3.3 and 5 V compatible logic supply
Thin profile QFN and TSSOP packages
Thermal shutdown circuitry
Short-to-ground protection
Shorted load protection
Low current Sleep mode, < 10 μA
Package:
24-pin TSSOP
with exposed thermal pad
(LP Package)
Approximate size
Description
The A4986 is a dual DMOS full-bridge stepper motor driver
with parallel input communication and overcurrent protection.
Each full-bridge output is rated up to 35 V and ±2 A.
The A4986 includes fixed off-time pulse width modulation
(PWM) current regulators, along with 2- bit nonlinear DACs
(digital-to-analog converters) that allow stepper motors to be
controlled in full, half, and quarter steps. The PWM current
regulator uses the Allegro® patented mixed decay mode for
reduced audible motor noise, increased step accuracy, and
reduced power dissipation.
Internal synchronous rectification control circuitry is provided
to improve power dissipation during PWM operation.
The outputs are protected from shorted load and short-to-
ground events, which protect the driver and associated circuitry
from thermal damage or flare-ups. Other protection features
include thermal shutdown with hysteresis, undervoltage lockout
(UVLO) and crossover current protection. Special power-up
sequencing is not required.
The A4986 is supplied in a 24-pin TSSOP (LP) with exposed
thermal pad for enhanced thermal performance. It has a
0.65 pitch and an overall package height of 1.2 mm. It is lead
(Pb) free, with 100% matte tin leadframe plating.
Typical Application Diagram
Microcontroller or
Controller Logic
VDD
0.22 μF
0.1 μF
0.1 μF
0.22 μF
VREG ROSC CP1
VDD
CP2
VCP VBB1
VBB2
SLEEP
IN01
IN02
PH1
IN11
IN12
PH2
VREF
A4986
OUT1A
OUT1B
SENSE1
GND
OUT2A
GND
OUT2B
SENSE2
100 μF
4986-DS




A4986 pdf, 반도체, 판매, 대치품
A4986
DMOS Dual Full-Bridge PWM Motor Driver
with Overcurrent Protection
ELECTRICAL CHARACTERISTICS1 at TA = 25°C, VBB = 35 V (unless otherwise noted)
Characteristics
Symbol
Test Conditions
Min. Typ.2 Max. Units
Output Drivers
Load Supply Voltage Range
Logic Supply Voltage Range
Output On Resistance
Body Diode Forward Voltage
Motor Supply Current
Logic Supply Current
VBB
VDD
RDSON
VF
IBB
IDD
Operating
During Sleep Mode
Operating
Source Driver, IOUT = –1.5 A
Sink Driver, IOUT = 1.5 A
Source Diode, IF = –1.5 A
Sink Diode, IF = 1.5 A
fPWM < 50 kHz
Operating, outputs disabled
Sleep Mode
fPWM < 50 kHz
Outputs off
Sleep Mode
8 – 35 V
0 – 35 V
3.0 – 5.5 V
– 320 430 mΩ
– 320 430 mΩ
– – 1.3 V
– – 1.3 V
– – 4 mA
– – 2 mA
– – 10 μA
– – 8 mA
– – 5 mA
– – 10 μA
Control Logic
Logic Input Voltage
Logic Input Current
Logic Input Pull-down
Logic Input Hysteresis
Blank Time
Fixed Off-Time
Reference Input Voltage Range
Reference Input Current
Current Trip-Level Error3
Crossover Dead Time
Protection
Overcurrent Protection Threshold
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
VDD Undervoltage Lockout
VDD Undervoltage Hysteresis
VIN(1)
VIN(0)
IIN(1)
IIN(0)
RIN02
RIN12
VHYS(IN)
tBLANK
tOFF
VREF
IREF
errI
tDT
VIN = VDD 0.7
VIN = VDD 0.3
As a % of VDD
OSC = VDD or GND
ROSC = 25 kΩ
VREF = 2 V, %ITripMAX = 33.3%
VREF = 2 V, %ITripMAX = 66.7%
VREF = 2 V, %ITripMAX = 100.00%
IOCPST
TTSD
TTSDHYS
VDDUVLO
VDDUVLOHYS
VDD rising
VDD 0.7
–20
–20
5
0.7
20
23
0
–3
100
<1.0
<1.0
100
50
11
1
30
30
0
475
VDD 0.3
20
20
19
1.3
40
37
4
3
±15
±5
±5
800
V
V
μA
μA
kΩ
kΩ
%
μs
μs
μs
V
μA
%
%
%
ns
2.1 – – A
– 165 –
°C
– 15 – °C
2.7 2.8 2.9
V
– 90 – mV
1For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
2Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual
units, within the specified maximum and minimum limits.
3VERR = [(VREF/8) – VSENSE] / (VREF/8).
Allegro MicroSystems, Inc.
4
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com

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A4986 전자부품, 판매, 대치품
A4986
DMOS Dual Full-Bridge PWM Motor Driver
with Overcurrent Protection
source-side FET gates. A 0.1 μF ceramic capacitor, should be
connected between CP1 and CP2. In addition, a 0.1 μF ceramic
capacitor is required between VCP and VBB, to act as a reservoir
for operating the high-side FET gates.
Capacitor values should be Class 2 dielectric ±15% maximum,
or tolerance R, according to EIA (Electronic Industries Alliance)
specifications.
VREG (VREG). This internally-generated voltage is used to oper-
ate the sink-side FET outputs. The VREG pin must be decoupled
with a 0.22 μF ceramic capacitor to ground. VREG is internally
monitored. In the case of a fault condition, the FET outputs of the
A4986 are disabled.
Capacitor values should be Class 2 dielectric ±15% maximum,
or tolerance R, according to EIA (Electronic Industries Alliance)
specifications.
Shutdown. In the event of a fault, overtemperature (excess TJ)
or an undervoltage (on VCP), the FET outputs of the A4986 are
disabled until the fault condition is removed. At power-on, the
UVLO (undervoltage lockout) circuit disables the FET outputs
and resets the translator to the Home state.
Sleep Mode ( ¯S¯¯L¯¯E¯¯E¯¯P¯ ). To minimize power consumption
when the motor is not in use, this input disables much of the
internal circuitry including the output FETs, current regulator, and
charge pump. A logic low on the SLEEP pin puts the A4986 into
Sleep mode. When emerging from Sleep mode, in order to allow
the charge pump to stabilize, provide a delay of 1 ms before issu-
ing a logic command.
Mixed Decay Operation. The bridge operates in Mixed
Decay mode, as shown in figures 5 through 7. As the trip point
is reached, the A4986 initially goes into a fast decay mode for
31.25% of the off-time, tOFF. After that, it switches to Slow Decay
mode for the remainder of tOFF. A timing diagram for this feature
appears in figure 4.
Synchronous Rectification. When a PWM-off cycle is
triggered by an internal fixed-off time cycle, load current recir-
culates in Mixed Decay mode. This synchronous rectification
feature turns on the appropriate FETs during current decay, and
effectively shorts out the body diodes with the low FET RDS(ON).
This reduces power dissipation significantly, and can eliminate
the need for external Schottky diodes in many applications. Syn-
chronous rectification turns off when the load current approaches
zero (0 A), preventing reversal of the load current.
5 A / div.
Fault
latched
t
Figure 1. Short-to-ground event
5 A / div.
Fixed off-time
t
Figure 2. Shorted load (OUTxA OUTxB) in
Slow decay mode
5 A / div.
Fixed off-time
Fast decay portion
(direction change)
t
Figure 3. Shorted load (OUTxA OUTxB) in Mixed decay mode
Allegro MicroSystems, Inc.
7
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com

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