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25P10 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 25P10
기능 1 Mbit Low Voltage Paged Flash Memory
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25P10 데이터시트, 핀배열, 회로
M25P10
1 Mbit Low Voltage Paged Flash Memory
With 20 MHz Serial SPI Bus Interface
PRELIMINARY DATA
s 1 Mbit PAGED Flash Memory
s 128 BYTE PAGE PROGRAM IN 3 ms TYPICAL
s 256 Kbit SECTOR ERASE IN 1 s TYPICAL
s BULK ERASE IN 2 s TYPICAL
s SINGLE 2.7 V to 3.6 V SUPPLY VOLTAGE
s SPI BUS COMPATIBLE SERIAL INTERFACE
s 20 MHz CLOCK RATE AVAILABLE
s SUPPORTS POSITIVE CLOCK SPI MODES
s DEEP POWER DOWN MODE (1 µA TYPICAL)
s ELECTRONIC SIGNATURE
s 10,000 ERASE/PROG CYCLES PER SECTOR
s 20 YEARS DATA RETENTION
s –40 TO 85°C TEMPERATURE RANGE
DESCRIPTION
The M25P10 is an 1 Mbit Paged Flash Memory
fabricated with STMicroelectronics High
Endurance CMOS technology. The memory is
accessed by a simple SPI bus compatible serial
interface. The bus signals are a serial clock input
(C), a serial data input (D) and a serial data output
(Q).
The device connected to the bus is selected when
the chip select input (S) goes low. Data is clocked
in during the low to high transition of clock C, data
8
1
SO8 (MN)
150 mil width
8
1
SO8 (MW)
200 mil width
Figure 1. Logic Diagram
VCC
Table 1. Signal Names
C Serial Clock
D Serial Data Input
Q Serial Data Output
S Chip Select
W Write Protect
HOLD
Hold
VCC Supply Voltage
VSS Ground
D
C
S
W
HOLD
M25P10
VSS
Q
AI03744
June 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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25P10 pdf, 반도체, 판매, 대치품
M25P10
Figure 5. M25P10-Compatible SPI Modes
CPOL CPHA
00
C
11
C
D or Q
MSB
LSB
AI01438
Clock Polarity (CPOL) and Clock Phase
(CPHA) with SPI Bus
As shown in Figure 5, the M25P10 can be driven
by a microcontroller with its SPI peripheral running
in either of the two following modes: (CPOL,
CPHA) = (’0’, ’0’) or (CPOL, CPHA) = (’1’, ’1’). For
these two modes, input data is latched in by the
low to high transition of clock C, and output data is
available from the high to low transition of Clock
(C).The difference between (CPOL, CPHA) = (0,
0) and (CPOL, CPHA) = (1, 1) is the clock polarity
when in stand-by: C remains at ’0’ for (CPOL,
CPHA) = (0, 0) and C remains at ’1’ for (CPOL,
CPHA) = (1, 1) when there is no data transfer.
MEMORY ORGANIZATION
The memory is organized in 131,072 words of 8
bits each. The device features 1,024 pages of 128
bytes each. Each page can be individually
programmed (bits are programmed from ‘1’ to ’0’
state).
The device is also organized in 4 sectors of
262,144 bits (32,768 x 8 bits) each.The device is
Sector or Bulk Erasable but not Page Erasable
(bits are erased from ’0’ to ’1’ state).
OPERATIONS
All instructions, addresses and data are shifted in
and out of the chip MSB first. Data input (D) is
sampled on the first rising edge of clock (C) after
the chip select (S) goes low. Prior to any
Table 4. Memory Organization
Sector
Address Range
3
18000h
1FFFFh
2
10000h
17FFFh
1
08000h
0FFFFh
0
00000h
07FFFh
Table 3. Protection Features
W SRWD
Status Register (SR)
Data Bytes (Software
Protected Area by BPi bits)
Mode
Data Bytes (Unprotected
Area)
X
0
Writeable after setting WEL
Software protected by the BPi
bits of the Status Register
SPM
Paged Programmable and
Sector Erasable
1
1
Writeable after setting WEL
Software protected by the BPi
bits of the Status Register
SPM
Paged Programmable and
Sector Erasable
01
Hardware protected
Hardware protected by the
BPi bits of the Status Register
and the W pin
HPM
Note: 1. SPM: Software Protected Mode.
2. HPM: Hardware Protected Mode.
3. BPi: Bits BP0 and BP1 of the Status Register.
4. WEL: Write Enable Latch of the Status Register.
5. W: Write Protect Input Pin.
6. SRWD: Status Register Write Disable Bits of the Status Register.
7. The device is Bulk Erasable if, and only if, (BP0, BP1) = (0, 0), (see Bulk Erase paragraph).
Paged Programmable and
Sector Erasable
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25P10 전자부품, 판매, 대치품
Figure 8. WRDI: Reset Write Enable Latch Sequence
S
01234567
C
INSTRUCTION
D
HIGH IMPEDANCE
Q
AI03750
M25P10
If more than 128 bytes are sent to the device,
previously latched data are discarded and the last
128 data bytes are guaranteed to be programmed
correctly within the same page. If less than 128
Data bytes are sent to device; they are correctly
programmed at the requested addresses without
having any effects on the other bytes of the same
Page.
The device must be deselected just after the
eighth bit of the last data byte has been latched in.
If not, the Page Program instruction is not
executed. As soon as the device is deselected, the
self-timed Page Program cycle (tPP) is initiated.
While the Page Program cycle is in progress, the
status register may be read to check the WIP bit
value. WIP is high during the self-timed Page
Program cycle and is low when it is completed.
When the cycle is completed, the write enable
latch (WEL) is reset.
A Page Program instruction applied to a Page
which is software protected by the BPi bits (see
Table 4 and Table 5) is not initiated.
The timing sequence is shown in Figure 12.
Write Enable (WREN) and Write Disable (WRDI)
The Write Enable Latch must be set prior to every
Page Program (PP), Sector Erase (SE), Bulk
Erase (BE) and Write Status Register (WRSR)
operation. The WREN instruction, whose timing
sequence is shown in Figure 7, will set the latch
and the WRDI instruction, whose timing sequence
is shown in Figure 8, will reset the latch.
The Write Enable Latch is reset under the
following conditions:
– Power on
– WRDI instruction completion
– WRSR instruction completion
– Page Program instruction completion
– Sector Erase instruction completion
– Bulk Erase instruction completion.
After completion of either WREN or WRDI
instruction, the chip enters a wait state and waits
for a deselect.
Figure 9. RDSR: Read Status Register Sequence
S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C
INSTRUCTION
D
STATUS REG. OUT
STATUS REG. OUT
HIGH IMPEDANCE
Q 76543210765432107
MSB
MSB
MSB
AI02031
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