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PSMN0R7-25YLD 데이터시트 PDF




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부품번호 PSMN0R7-25YLD 기능
기능 N-channel MOSFET
제조업체 NXP Semiconductors
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PSMN0R7-25YLD 데이터시트, 핀배열, 회로
PSMN0R7-25YLD
N-channel 25 V, 0.7 mΩ logic level MOSFET in LFPAK56
using NextPowerS3 Technology
15 April 2015
Objective data sheet
1. General description
Logic level gate drive N-channel enhancement mode MOSFET in LFPAK56 package.
NextPowerS3 portfolio utilising NXP's unique "SchottkyPlus" technology delivers
high efficiency, low spiking performance usually associated with MOSFETS with an
integrated Schottky or Schottky-like diode but without problematic high leakage current.
NextPowerS3 is particularly suited to high efficiency applications at high switching
frequencies.
2. Features and benefits
Ultra low QG, QGD and QOSS for high system efficiency, especially at higher switching
frequencies
Superfast switching with soft-recovery; s-factor > 1
Low spiking and ringing for low EMI designs
Unique "SchottkyPlus" technology; Schottky-like performance with < 1 μA leakage at
25 °C
Optimised for 4.5 V gate drive
Low parasitic inductance and resistance
High reliability clip bonded and solder die attach Power SO8 package; no glue, no
wire bonds, qualified to 150 °C
Wave solderable; exposed leads for optimal visual solder inspection
3. Applications
On-board DC:DC solutions for server and telecommunications
Secondary-side synchronous rectification in telecommunication applications
Voltage regulator modules (VRM)
Point-of-Load (POL) modules
Power delivery for V-core, ASIC, DDR, GPU, VGA and system components
Brushed and brushless motor control
Power OR-ing
4. Quick reference data
Table 1.
Symbol
VDS
ID
Ptot
Quick reference data
Parameter
Conditions
drain-source voltage 25 °C ≤ Tj ≤ 150 °C
drain current
Tmb = 25 °C; VGS = 10 V
total power dissipation Tmb = 25 °C; Fig. 1
Min Typ Max Unit
- - 25 V
[1] - - 100 A
- - 291 W
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PSMN0R7-25YLD pdf, 반도체, 판매, 대치품
NXP Semiconductors
120
Pder
(%)
80
PSMN0R7-25YLD
N-channel 25 V, 0.7 mΩ logic level MOSFET in LFPAK56 using
NextPowerS3 Technology
03ne36
40
0
0 50 100 150 200
Tmb (°C)
Fig. 1. Normalized total power dissipation as a function of mounting base temperature
8. Thermal characteristics
Table 5.
Symbol
Rth(j-mb)
Rth(j-a)
Thermal characteristics
Parameter
thermal resistance
from junction to
mounting base
thermal resistance
from junction to
ambient
Conditions
Fig. 2
Fig. 3
Min Typ Max Unit
- 0.35 0.43 K/W
- 50 - K/W
- 125 - K/W
aaa-005750
aaa-005751
Fig. 2.
PCB layout for thermal resistance junction to
ambient 1” square pad; FR4 Board; 2oz copper
Fig. 3.
PCB layout for thermal resistance junction to
ambient minimum footprint; FR4 Board; 2oz
copper
PSMN0R7-25YLD
Objective data sheet
All information provided in this document is subject to legal disclaimers.
15 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved
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PSMN0R7-25YLD 전자부품, 판매, 대치품
NXP Semiconductors
PSMN0R7-25YLD
N-channel 25 V, 0.7 mΩ logic level MOSFET in LFPAK56 using
NextPowerS3 Technology
10. Package outline
Plastic single-ended surface-mounted package (LFPAK56); 4 leads
SOT1023
E AA
b1 c1
E1
b2
(3x)
D
H
mounting
base
D1
L
1234
e b wA
X
c
A1 C
θ
detail X Lp y C
Dimensions
0 2.5 5 mm
scale
Unit A A1 b b1 b2 c c1 D(1) D1(1) E(1) E1(1) e H
max 1.10 0.15 0.50 4.41
0.25 0.30 4.70 4.45 5.30 3.7
6.2
mm nom
0.85
1.27
min 0.95 0.00 0.35 3.62
0.19 0.24 4.45
4.95 3.5
5.9
Note
1. Plastic or metal protrusions of 0.15 mm per side are not included.
Outline
References
version
IEC
JEDEC
JEITA
L Lp w y
1.3 0.85
0.25 0.1
0.8 0.40
European
projection
SOT1023
θ
8°
0°
Fig. 6. Package outline LFPAK56; Power-SO8 (SOT1023)
sot1023_po
Issue date
11-12-09
13-03-05
PSMN0R7-25YLD
Objective data sheet
All information provided in this document is subject to legal disclaimers.
15 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved
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PSMN0R7-25YLD

N-channel MOSFET

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