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EFM8BB1 데이터시트 PDF




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EFM8BB1 데이터시트, 핀배열, 회로
EFM8 Busy Bee Family
EFM8BB1 Data Sheet
The EFM8BB1, part of the Busy Bee family of MCUs, is a multi-
purpose line of 8-bit microcontrollers with a comprehensive feature
set in small packages.
These devices offer high-value by integrating advanced analog and communication pe-
ripherals into small packages, making them ideal for space-constrained applications.
With an efficient 8051 core, enhanced pulse-width modulation, and precision analog, the
EFM8BB1 family is also optimal for embedded applications.
EFM8BB1 applications include the following:
• Motor control
• Consumer electronics
• Sensor controllers
• Medical equipment
• Lighting systems
• I/O port expander
KEY FEATURES
• Pipelined 8-bit C8051 core with 25 MHz
maximum operating frequency
• Up to 18 multifunction, 5 V tolerant I/O pins
• One 12-bit Analog to Digital converter
(ADC)
• Two low-current analog comparators
• Integrated temperature sensor
• 3-channel enhanced PWM / PCA
• Four 16-bit timers
• UART, SPI and SMBus/I2C
• Priority crossbar for flexible pin mapping
Core / Memory
CIP-51 8051 Core
(25 MHz)
Clock Management
External CMOS
Oscillator
High Frequency
RC Oscillator
Energy Management
Internal LDO
Regulator
Power-On Reset
Flash Program
Memory
(up to 8 KB)
RAM Memory
(up to 512 bytes)
Debug Interface
with C2
Serial Interfaces
UART
SPI
I2C / SMBus
I/O Ports
External
Interrupts
Pin Reset
General Purpose I/O
Low Frequency
RC Oscillator
8-bit SFR bus
Timers and Triggers
16-bit
Timers
PCA/PWM
Watchdog Timer
Brown-Out Detector
Analog Interfaces
ADC
Analog
Comparators
Internal Voltage Reference
Security
16-bit CRC
Lowest power mode with peripheral operational:
Normal
Idle
Shutdown
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.1




EFM8BB1 pdf, 반도체, 판매, 대치품
3. System Overview
3.1 Introduction
EFM8BB1 Data Sheet
System Overview
C2CK/RSTb
Power On
Reset
Reset
Debug /
Programming
Hardware
C2D
CIP-51 8051 Controller
Core
8/4/2 KB ISP Flash
Program Memory
256 Byte SRAM
256 Byte XRAM
VDD
GND
Power Net
Independent
Watchdog Timer
SYSCLK
System Clock
Configuration
EXTCLK
24.5 MHz
2%
Oscillator
Low-Freq.
Oscillator
CMOS
Oscillator
Input
SFR
Bus
Port I/O Configuration
Digital Peripherals
UART
Timers 0,
1, 2, 3
3-ch PCA
I2C /
SMBus
SPI
CRC
Priority
Crossbar
Decoder
Crossbar Control
Analog Peripherals
Internal
Reference
VDD
VREF
12/10 bit
ADC
VDD
Temp
Sensor
+-+-
2 Comparators
Figure 3.1. Detailed EFM8BB1 Block Diagram
Port 0
Drivers
Port 1
Drivers
Port 2
Driver
P0.n
P1.n
P2.n
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.1 | 3

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EFM8BB1 전자부품, 판매, 대치품
3.6 Communications and Other Digital Peripherals
EFM8BB1 Data Sheet
System Overview
Universal Asynchronous Receiver/Transmitter (UART0)
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support
allows a wide range of clock sources to generate standard baud rates. Received data buffering allows UART0 to start reception of a
second incoming data byte before software has finished reading the previous data byte.
The UART module provides the following features:
• Asynchronous transmissions and receptions
• Baud rates up to SYSCLK/2 (transmit) or SYSCLK/8 (receive)
• 8- or 9-bit data
• Automatic start and stop generation
Serial Peripheral Interface (SPI0)
The serial peripheral interface (SPI) module provides access to a flexible, full-duplex synchronous serial bus. The SPI can operate as a
master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select
(NSS) signal can be configured as an input to select the SPI in slave mode, or to disable master mode operation in a multi-master
environment, avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be
configured as a firmware-controlled chip-select output in master mode, or disabled to reduce the number of pins required. Additional
general purpose port I/O pins can be used to select multiple slave devices in master mode.
The SPI module includes the following features:
• Supports 3- or 4-wire operation in master or slave modes.
• Supports external clock frequencies up to SYSCLK / 2 in master mode and SYSCLK / 10 in slave mode.
• Support for four clock phase and polarity options.
• 8-bit dedicated clock clock rate generator.
• Support for multiple masters on the same data lines.
System Management Bus / I2C (SMB0)
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specifica-
tion, version 1.1, and compatible with the I2C serial bus.
The SMBus module includes the following features:
• Standard (up to 100 kbps) and Fast (400 kbps) transfer speeds.
• Support for master, slave, and multi-master modes.
• Hardware synchronization and arbitration for multi-master mode.
• Clock low extending (clock stretching) to interface with faster masters.
• Hardware support for 7-bit slave and general call address recognition.
• Firmware support for 10-bit slave address decoding.
• Ability to inhibit all slave states.
• Programmable data setup/hold times.
16-bit CRC (CRC0)
The cyclic redundancy check (CRC) module performs a CRC using a 16-bit polynomial. CRC0 accepts a stream of 8-bit data and posts
the 16-bit result to an internal register. In addition to using the CRC block for data manipulation, hardware can automatically CRC the
flash contents of the device.
The CRC module is designed to provide hardware calculations for flash memory verification and communications protocols. The CRC
module supports the standard CCITT-16 16-bit polynomial (0x1021), and includes the following features:
• Support for CCITT-16 polynomial
• Byte-level bit reversal
• Automatic CRC of flash contents on one or more 256-byte blocks
• Initial seed selection of 0x0000 or 0xFFFF
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.1 | 6

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