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PDF EFM8BB2 Data sheet ( Hoja de datos )
| Número de pieza | EFM8BB2 | |
| Descripción | microcontrollers | |
| Fabricantes | Silicon Laboratories | |
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EFM8 Busy Bee Family
EFM8BB2 Data Sheet
The EFM8BB2, part of the Busy Bee family of MCUs, is a multi-
purpose line of 8-bit microcontrollers with a comprehensive feature
set in small packages.
These devices offer high-value by integrating advanced analog and enhanced high-
speed communication peripherals into small packages, making them ideal for space-con-
strained applications. With an efficient 8051 core, enhanced pulse-width modulation, and
precision analog, the EFM8BB2 family is also optimal for embedded applications.
EFM8BB2 applications include the following:
• Motor control
• Consumer electronics
• Sensor controllers
• Medical equipment
• Lighting systems
• High-speed communication hub
KEY FEATURES
• Pipelined 8-bit C8051 core with 50 MHz
maximum operating frequency
• Up to 22 multifunction, 5 V tolerant I/O pins
• One 12-bit Analog to Digital converter
(ADC)
• Two Low-current analog comparators with
build-in DAC as reference input
• Integrated temperature sensor
• 3-channel PWM / PCA with special
hardware kill/safe state capability
• Five 16-bit timers
• Two UARTs, SPI, SMBus/I2C master/slave
and I2C slave
• Priority crossbar for flexible pin mapping
Core / Memory
CIP-51 8051 Core
(50 MHz)
Clock Management
External CMOS
Oscillator
High Frequency
49 MHz RC
Oscillator
Energy Management
Internal LDO
Regulator
Power-On Reset
Flash Program
Memory
(16 KB)
RAM Memory
(2304 bytes)
Debug Interface
with C2
Low Frequency
RC Oscillator
High Frequency
24.5 MHz RC
Oscillator
Brown-Out
Detector
5 V-to 3.3 V LDO
Regulator
Serial Interfaces
2 x UART
SPI
I2C / SMBus
High-Speed
I2C Slave
I/O Ports
External
Interrupts
Pin Reset
General
Purpose I/O
Pin Wakeup
8-bit SFR bus
Timers and Triggers
Timer
0/1/2
PCA/PWM
Watchdog
Timer
Timer 3/4
Lowest power mode with peripheral operational:
Normal
Idle
Suspend
Snooze
Shutdown
Analog Interfaces
ADC
Comparator 0
Comparator 1
Internal
Voltage
Reference
Security
16-bit CRC
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.1
1 page  
EFM8BB2 Data Sheet
System Overview
3.2 Power
All internal circuitry draws power from the VDD supply pin. External I/O pins are powered from the VIO supply voltage (or VDD on devi-
ces without a separate VIO connection), while most of the internal circuitry is supplied by an on-chip LDO regulator. Control over the
device power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when
not in use and placed in low power mode. Digital peripherals, such as timers and serial buses, have their clocks gated off and draw little
power when they are not in use.
Table 3.1. Power Modes
Power Mode
Normal
Idle
Suspend
Stop
Snooze
Shutdown
Details
Core and all peripherals clocked and fully operational
• Core halted
• All peripherals clocked and fully operational
• Code resumes execution on wake event
Mode Entry
—
Set IDLE bit in PCON0
Wake-Up Sources
—
Any interrupt
• Core and peripheral clocks halted
• HFOSC0 and HFOSC1 oscillators stopped
• Regulators in normal bias mode for fast wake
• Timer 3 and 4 may clock from LFOSC0
• Code resumes execution on wake event
1. Switch SYSCLK to
HFOSC0
2. Set SUSPEND bit in
PCON1
• Timer 4 Event
• SPI0 Activity
• I2C0 Slave Activity
• Port Match Event
• Comparator 0 Falling
Edge
• All internal power nets shut down
• 5 V regulator remains active (if enabled)
• Internal 1.8 V LDO on
• Pins retain state
• Exit on any reset source
1. Clear STOPCF bit in
REG0CN
2. Set STOP bit in
PCON0
Any reset source
• Core and peripheral clocks halted
• HFOSC0 and HFOSC1 oscillators stopped
• Regulators in low bias current mode for energy sav-
ings
• Timer 3 and 4 may clock from LFOSC0
• Code resumes execution on wake event
1. Switch SYSCLK to
HFOSC0
2. Set SNOOZE bit in
PCON1
• Timer 4 Event
• SPI0 Activity
• I2C0 Slave Activity
• Port Match Event
• Comparator 0 Falling
Edge
• All internal power nets shut down
• 5 V regulator remains active (if enabled)
• Internal 1.8 V LDO off to save energy
• Pins retain state
• Exit on pin or power-on reset
1. Set STOPCF bit in
REG0CN
2. Set STOP bit in
PCON0
• RSTb pin reset
• Power-on reset
3.3 I/O
Digital and analog resources are externally available on the device’s multi-purpose I/O pins. Port pins P0.0-P2.3 can be defined as gen-
eral-purpose I/O (GPIO), assigned to one of the internal digital resources through the crossbar or dedicated channels, or assigned to an
analog function. Port pins P3.0 and P3.1 can be used as GPIO. Additionally, the C2 Interface Data signal (C2D) is shared with P3.0.
The port control block offers the following features:
• Up to 22 multi-functions I/O pins, supporting digital and analog functions.
• Flexible priority crossbar decoder for digital peripheral assignment.
• Two drive strength settings for each port.
• Two direct-pin interrupt sources with dedicated interrupt vectors (INT0 and INT1).
• Up to 20 direct-pin interrupt sources with shared interrupt vector (Port Match).
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.1 | 4
5 Page 
EFM8BB2 Data Sheet
System Overview
3.10 Bootloader
All devices come pre-programmed with a UART bootloader. This bootloader resides in the code security page and last page of code
flash; it can be erased if it is not needed.
The byte before the Lock Byte is the Bootloader Signature Byte. Setting this byte to a value of 0xA5 indicates the presence of the boot-
loader in the system. Any other value in this location indicates that the bootloader is not present in flash.
When a bootloader is present, the device will jump to the bootloader vector after any reset, allowing the bootloader to run. The boot-
loader then determines if the device should stay in bootload mode or jump to the reset vector located at 0x0000. When the bootloader
is not present, the device will jump to the reset vector of 0x0000 after any reset.
0xFFFF
0xFFC0
0xFFBF
0xFC00
0xFBFF
0xFBFE
Read-Only
Reserved
Lock Byte
Bootloader Signature Byte
0xFBC0
0xFBBF
0xF800
0xF7FF
0x4000
0x3FFF
Code Security Page
64 Bytes
Nonvolatile Data
Reserved
Bootloader Vector
16 KB Code
(32 x 512 Byte pages)
0x0000
Reset Vector
Figure 3.2. Flash Memory Map with Bootloader—16 kB Devices
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.1 | 10
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet EFM8BB2.PDF ] | |
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