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PDF EFM8UB1 Data sheet ( Hoja de datos )
| Número de pieza | EFM8UB1 | |
| Descripción | microcontrollers | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
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EFM8 Universal Bee Family
EFM8UB1 Data Sheet
The EFM8UB1, part of the Universal Bee family of MCUs, is a
multi-purpose line of 8-bit microcontrollers with USB feature set in
small packages.
These devices offer high value by integrating an innovative energy-smart USB peripheral
interface, charger detect circuit, 8 kV ESD protection, and enhanced high speed commu-
nication interfaces into small packages, making them ideal for space-constrained USB
applications. With an efficient 8051 core and precision analog, the EFM8UB1 family is
also optimal for embedded applications.
EFM8UB1 applications include the following:
• USB I/O controls, dongles
• High-speed communication bridge
• Consumer electronics
• Medical equipment
KEY FEATURES
• Pipelined 8-bit C8051 core with 50 MHz
maximum operating frequency
• Up to 22 multifunction, 5 V tolerant I/O pins
• Low Energy USB with full- and low-speed
support saves up to 90% of the USB
energy
• USB charger detect circuit (USB-BCS 1.2
compliant)
• One 12-bit ADC and two analog
comparators with internal voltage DAC as
reference input
• Five 16-bit timers
• Two UARTs, SPI, SMBus/I2C master/slave
and I2C slave
• Priority crossbar for flexible pin mapping
Core / Memory
CIP-51 8051 Core
(50 MHz)
Clock Management
External CMOS
Oscillator
High Frequency
48 MHz RC
Oscillator
Energy Management
Internal LDO
Regulator
Power-On Reset
Flash Program
Memory
(up to 16 KB)
RAM Memory
(2304 bytes)
Debug Interface
with C2
Low Frequency
RC Oscillator
High Frequency
24.5 MHz RC
Oscillator
Brown-Out
Detector
5 V-to 3.3 V LDO
Regulator
Serial Interfaces
2 x UART
SPI
I2C / SMBus
USB
High-Speed I2C Slave
I/O Ports
External
Interrupts
Pin Reset
General
Purpose I/O
Pin Wakeup
8-bit SFR bus
Timers and Triggers
Timer
0/1/2
PCA/PWM
Watchdog
Timer
Timer 3/4
Lowest power mode with peripheral operational:
Normal
Idle
Suspend
Snooze
Shutdown
Analog Interfaces
ADC
Comparator 0
Comparator 1
Internal
Voltage
Reference
Security
16-bit CRC
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Rev. 1.1
1 page  
EFM8UB1 Data Sheet
System Overview
3.2 Power
All internal circuitry draws power from the VDD supply pin. External I/O pins are powered from the VIO supply voltage (or VDD on devi-
ces without a separate VIO connection), while most of the internal circuitry is supplied by an on-chip LDO regulator. Control over the
device power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when
not in use and placed in low power mode. Digital peripherals, such as timers and serial buses, have their clocks gated off and draw little
power when they are not in use.
Table 3.1. Power Modes
Power Mode
Normal
Idle
Suspend
Stop
Snooze
Shutdown
Details
Core and all peripherals clocked and fully operational
• Core halted
• All peripherals clocked and fully operational
• Code resumes execution on wake event
Mode Entry
—
Set IDLE bit in PCON0
Wake-Up Sources
—
Any interrupt
• Core and peripheral clocks halted
• HFOSC0 and HFOSC1 oscillators stopped
• Regulators in normal bias mode for fast wake
• Timer 3 and 4 may clock from LFOSC0
• Code resumes execution on wake event
1. Switch SYSCLK to
HFOSC0
2. Set SUSPEND bit in
PCON1
• USB0 Bus Activity
• Timer 4 Event
• SPI0 Activity
• I2C0 Slave Activity
• Port Match Event
• Comparator 0 Falling
Edge
• All internal power nets shut down
• 5V regulator remains active (if enabled)
• Internal 1.8 V LDO on
• Pins retain state
• Exit on any reset source
1. Clear STOPCF bit in
REG0CN
2. Set STOP bit in
PCON0
Any reset source
• Core and peripheral clocks halted
• HFOSC0 and HFOSC1 oscillators stopped
• Regulators in low bias current mode for energy sav-
ings
• Timer 3 and 4 may clock from LFOSC0
• Code resumes execution on wake event
1. Switch SYSCLK to
HFOSC0
2. Set SNOOZE bit in
PCON1
• USB0 Bus Activity
• Timer 4 Event
• SPI0 Activity
• I2C0 Slave Activity
• Port Match Event
• Comparator 0 Falling
Edge
• All internal power nets shut down
• 5V regulator remains active (if enabled)
• Internal 1.8 V LDO off to save energy
• Pins retain state
• Exit on pin or power-on reset
1. Set STOPCF bit in
REG0CN
2. Set STOP bit in
PCON0
• RSTb pin reset
• Power-on reset
3.3 I/O
Digital and analog resources are externally available on the device’s multi-purpose I/O pins. Port pins P0.0-P2.3 can be defined as gen-
eral-purpose I/O (GPIO), assigned to one of the internal digital resources through the crossbar or dedicated channels, or assigned to an
analog function. Port pins P3.0 and P3.1 can be used as GPIO. Additionally, the C2 Interface Data signal (C2D) is shared with P3.0.
The port control block offers the following features:
• Up to 22 multi-functions I/O pins, supporting digital and analog functions.
• Flexible priority crossbar decoder for digital peripheral assignment.
• Two drive strength settings for each port.
• Two direct-pin interrupt sources with dedicated interrupt vectors (INT0 and INT1).
• Up to 20 direct-pin interrupt sources with shared interrupt vector (Port Match).
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.1 | 4
5 Page 
EFM8UB1 Data Sheet
System Overview
3.8 Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur:
• The core halts program execution.
• Module registers are initialized to their defined reset values unless the bits reset only with a power-on reset.
• External port pins are forced to a known state.
• Interrupts and timers are disabled.
All registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a power-on reset. The
contents of RAM are unaffected during a reset; any previously stored data is preserved as long as power is not lost. The Port I/O latch-
es are reset to 1 in open-drain mode. Weak pullups are enabled during and after the reset. For Supply Monitor and power-on resets,
the RSTb pin is driven low until the device exits the reset state. On exit from the reset state, the program counter (PC) is reset, and the
system clock defaults to an internal oscillator. The Watchdog Timer is enabled, and program execution begins at location 0x0000.
Reset sources on the device include:
• Power-on reset
• External reset pin
• Comparator reset
• Software-triggered reset
• Supply monitor reset (monitors VDD supply)
• Watchdog timer reset
• Missing clock detector reset
• Flash error reset
• USB reset
3.9 Debugging
The EFM8UB1 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow flash programming and in-system debug-
ging with the production part installed in the end application. The C2 interface uses a clock signal (C2CK) and a bi-directional C2 data
signal (C2D) to transfer information between the device and a host system. See the C2 Interface Specification for details on the C2
protocol.
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.1 | 10
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet EFM8UB1.PDF ] | |
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