|
|
PDF EFM8UB2 Data sheet ( Hoja de datos )
| Número de pieza | EFM8UB2 | |
| Descripción | microcontrollers | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de EFM8UB2 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
EFM8 Universal Bee Family
EFM8UB2 Data Sheet
The EFM8UB2, part of the Universal Bee family of MCUs, is a
multi-purpose line of 8-bit microcontrollers with USB feature set.
These devices offer high value by integrating a USB peripheral interface with a high pre-
cision oscillator, clock recovery circuit, and integrated transceiver, making them ideal for
any full speed USB applications with no external components required. With an efficient
8051 core and precision analog, the EFM8UB2 family is also optimal for embedded ap-
plications.
EFM8UB2 applications include the following:
• USB I/O controls, dongles
• High-speed communication bridge
• Consumer electronics
• Medical equipment
KEY FEATURES
• Pipelined 8-bit 8051 MCU Core with 48
MHz maximum operating frequency
• Up to 40 multifunction I/O pins
• Crystal-less full speed/low speed USB 2.0
compliant controller with 1 KB buffer
memory
• One differential 10-bit ADC and two analog
comparators
• Internal 48 MHz oscillator with ±0.25%
accuracy with USB clock recovery supports
crystal-free USB and UART operation
• 2 UARTs, SPI, 2 SMBus/I2C serial
communications
Core / Memory
CIP-51 8051 Core
(48 MHz)
Flash Program
Memory
(up to 64 KB)
RAM Memory
(up to 4352 bytes)
Debug Interface
with C2
Serial Interfaces
2 x UART
SPI
2 x I2C /
SMBus
USB
I/O Ports
External
Interrupts
Pin Reset
General Purpose I/O
Lowest power mode with peripheral operational:
Normal
Idle
Suspend
Shutdown
Clock Management
External
Oscillator
High Frequency
48 MHz RC
Oscillator
Energy Management
Internal LDO
Regulator
Power-On Reset
Low Frequency
RC Oscillator
Brown-Out
Detector
5 V-to 3.3 V LDO
Regulator
8-bit SFR bus
Timers and Triggers
6 x Timers PCA/PWM
Watchdog Timer
Analog Interfaces
ADC
Comparator 0
Comparator 1
Internal
Voltage
Reference
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.2
1 page  
EFM8UB2 Data Sheet
System Overview
3.2 Power
All internal circuitry draws power from the VDD supply pin. External I/O pins are powered from the VIO supply voltage (or VDD on devi-
ces without a separate VIO connection), while most of the internal circuitry is supplied by an on-chip LDO regulator. Control over the
device power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when
not in use and placed in low power mode. Digital peripherals, such as timers and serial buses, have their clocks gated off and draw little
power when they are not in use.
Table 3.1. Power Modes
Power Mode
Normal
Idle
Suspend
Shutdown
Details
Core and all peripherals clocked and fully operational
• Core halted
• All peripherals clocked and fully operational
• Code resumes execution on wake event
• Core and peripheral clocks halted
• Code resumes execution on wake event
• All internal power nets shut down
• 5V regulator remains active (if enabled)
• Pins retain state
• Exit on pin or power-on reset
Mode Entry
—
Set IDLE bit in PCON0
1. Switch SYSCLK to
HFOSC0
2. Set SUSPEND bit in
HFO0CN
1. Set STOPCF bit in
REG01CN
2. Set STOP bit in
PCON0
Wake-Up Sources
—
Any interrupt
USB0 Bus Activity
• RSTb pin reset
• Power-on reset
3.3 I/O
Digital and analog resources are externally available on the device’s multi-purpose I/O pins. Port pins P0.0-P3.7 can be defined as gen-
eral-purpose I/O (GPIO), assigned to one of the internal digital resources through the crossbar or dedicated channels, or assigned to an
analog function. Port pins P4.0-P4.7 can be used as GPIO. Additionally, the C2 Interface Data signal (C2D) is shared with P3.0 on
some packages.
• Up to 40 multi-functions I/O pins, supporting digital and analog functions.
• Flexible priority crossbar decoder for digital peripheral assignment.
• Two direct-pin interrupt sources with dedicated interrupt vectors (INT0 and INT1) available on P0 pins.
3.4 Clocking
The CPU core and peripheral subsystem may be clocked by both internal and external oscillator resources. By default, the system
clock comes up running from the 48 MHz oscillator divided by 4, then divided by 8 (1.5 MHz).
• Provides clock to core and peripherals.
• 48 MHz internal oscillator (HFOSC0), accurate to ±1.5% over supply and temperature corners: accurate to +/- 0.25% when using
USB clock recovery.
• 80 kHz low-frequency oscillator (LFOSC0).
• External RC, C, CMOS, and high-frequency crystal clock options (EXTCLK) for QFP48 packages.
• External CMOS clock option (EXTCLK) for QFP32 and QFN32 packages.
• Internal oscillator has clock divider with eight settings for flexible clock scaling: 1, 2, 4, or 8.
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.2 | 4
5 Page 
EFM8UB2 Data Sheet
Electrical Specifications
Parameter
Symbol Test Condition
Min Typ Max Unit
ADC0 Supply Current
IADC
Operating at 500 ksps
VDD = 3.0 V
—
750 1000
μA
On-chip Precision Reference
IVREFP
— 75 — µA
Temperature Sensor
ITSENSE
— 35 — μA
Comparator 0 (CMP0, CMP1)
ICMP
CPMD = 11
CPMD = 10
— 1 — μA
— 4 — μA
CPMD = 01
— 10 — μA
CPMD = 00
— 20 — μA
Voltage Supply Monitor (VMON0) IVMON
— 15 50 μA
Regulator Bias Currents
IVREG
Both Regulators in Normal Mode
—
200
—
Both Regulators in Low Power
Mode
— 100 —
μA
μA
5 V Regulator Off, Internal LDO in
—
150
—
Low Power Mode
μA
USB (USB0) Full-Speed
IUSB
Active
— 8 — mA
Note:
1. Currents are additive. For example, where IDD is specified and the mode is not mutually exclusive, enabling the functions increa-
ses supply current by the specified amount.
2. Includes supply current from regulators, supply monitor, and High Frequency Oscillator.
3. Includes supply current from regulators, supply monitor, and Low Frequency Oscillator.
Table 4.3. Reset and Supply Monitor
Parameter
Symbol
VDD Supply Monitor Threshold
VVDDM
VDD Ramp Time
tRMP
Reset Delay from non-POR source tRST
RST Low Time to Generate Reset tRSTL
Missing Clock Detector Response tMCD
Time (final rising edge to reset)
VDD Supply Monitor Turn-On Time tMON
Test Condition
Time to VDD > 2.7 V
Time between release of reset
source and code execution
FSYSCLK >1 MHz
Table 4.4. Flash Memory
Min
2.60
—
—
15
80
—
Parameter
Symbol
Write Time1
tWRITE
Erase Time1
tERASE
VDD Voltage During Programming2 VPROG
Endurance (Write/Erase Cycles) NWE
Test Condition
One Byte
One Page
Min
10
10
2.7
10k
Typ
2.65
—
—
—
580
—
Typ
15
15
—
100k
Max Unit
2.70 V
1 ms
250 μs
— μs
800 μs
100 μs
Max Units
20 μs
22.5 ms
3.6 V
— Cycles
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.2 | 10
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet EFM8UB2.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| EFM8UB1 | microcontrollers | Silicon Laboratories |
| EFM8UB2 | microcontrollers | Silicon Laboratories |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |