Datasheet.kr   

8V44N4614 데이터시트 PDF




Integrated Device Technology에서 제조한 전자 부품 8V44N4614은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 8V44N4614 자료 제공

부품번호 8V44N4614 기능
기능 NG Jitter Attenuator and Clock Synthesizer
제조업체 Integrated Device Technology
로고 Integrated Device Technology 로고


8V44N4614 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 30 페이지수

미리보기를 사용할 수 없습니다

8V44N4614 데이터시트, 핀배열, 회로
FemtoClock® NG Jitter Attenuator and
Clock Synthesizer
8V44N4614
DATA SHEET
General Description
The 8V44N4614 is a FemtoClock® NG Clock Generator. The device
has been designed for frequency generation in high-performance
systems such wireless base-band boards, for instance to drive the
reference clock inputs of processors, PHY, switch and SerDes
devices. The device is very flexible in frequency programming. It
allows to generate the clock frequencies of 156.25MHz, 125MHz,
100MHz and 25MHz individually at three output banks. One output
bank supports configurable LVDS, LVPECL, the other two output
banks support LVCMOS output levels. All outputs are synchronized
on the incident rising edge, regardless of the selected output
frequency. Selective single-ended LVCMOS outputs can be
configured to invert the output phase, effectively forming differential
LVCMOS output pairs for noise reduction. The PLL reference signal
is either a 25MHz, 50MHz, 100MHz or 200MHz differential or
single-ended clock.
The device is optimized to deliver excellent period and cycle-to-cycle
jitter performance, combined with good phase noise performance,
and high power supply noise rejection.
The device is configured through an SPI serial interface. Outputs can
be configured to any of the available output frequencies. Two
hardware pins are available for selecting pre-set output enable/
disable configurations. In each of these pre-set configurations, each
output can be enabled/disabled individually. A separate test mode is
available for an increase or decrease of the output frequencies in
19.53125ppm steps independent on the input frequency. The device
is packaged in a lead-free (RoHS 6) 48-lead VFQFN package. The
extended temperature range supports wireless infrastructure,
telecommunication and networking end equipment requirements.
Features
Clock generator for wireless base-band systems
Drives reference clock inputs of processors, PHY, switch and
SerDes devices
FemtoClock® NG technology
Three low-skew, differential LVDS, LVPECL configurable clock
outputs
Ten low-skew, LVCMOS/LVTTL clock outputs
Input: 200MHz, 100MHz, 50MHz, 25MHz single-ended
(LVCMOS) or differential reference clock (LVDS, LVPECL)
Output clocks support 156.25MHz, 125MHz, 100MHz and 25MHz
Individual output disable (high-impedance)
Two sets of output enable configurations
PLL lock detect output
Test mode with frequency margining with 19.53125ppm steps
(range ±507.8125ppm)
LVCMOS (1.8V, JESD8-7A) compatible SPI programming
interface
Cycle-to-cycle jitter: 10ps (typical)
RMS period jitter: 1.6ps (typical)
Phase noise (12kHz - 20MHz): 0.40ps (typical)
3.3V core and output supply
-40°C to +85°C ambient operating temperature
Lead-free (RoHS 6) 48-lead VFQFN packaging
REVISION 1 02/25/15
1 ©2015 INTEGRATED DEVICE TECHNOLOGY, INC.




8V44N4614 pdf, 반도체, 판매, 대치품
8V44N4614 DATA SHEET
Table 1: Pin Descriptions (Continued)
Number
Name
Type
18
MISO
Output
19
VDDOB
Power
20 QB3 Output
21 QB2 Output
22 QB1 Output
23 QB0 Output
25
OENB
Input
Pulldown
26 DNU
27
OENA
Input
Pullup
28, 34
30
VDDOC
QC3
Power
Output
31
QC2
Output
32
QC1
Output
33
QC0
Output
36
TEST
Input
Pulldown
39
BYPASS
Input
Pulldown
41
VDDA
Power
42
LOCK
Output
44
nCLK
Input
Pullup /
Pulldown
45
CLK
Input
Pulldown
46
VDDI
Power
47
LCLK
Input
Pulldown
48
REFSEL
Input
Pulldown
VEE_EP
Power
Description
Serial Control Port SPI Mode Data Output. 1.8V LVCMOS (JESD8-7A)
output levels.
Supply voltage for the QB bank clock outputs (3.3V).
Single-ended clock output B3. Complementary to QB2 when configured as
inverted output. 3.3V LVCMOS/LVTTL output levels.
Single-ended clock output B2. 3.3V LVCMOS/LVTTL output levels.
Single-ended clock output B1. Complementary to QB0 when configured as
inverted output. 3.3V LVCMOS/LVTTL output levels.
Single-ended clock output B0. 3.3V LVCMOS/LVTTL output levels.
Output enable (active high). 3.3V LVCMOS/LVTTL interface levels. See
Table 3J for function.
Do not connect and do not use.
Output enable (active high). 3.3V LVCMOS/LVTTL interface levels. See
Table 3J for function.
Supply voltage for the QC bank clock outputs (3.3V)
Single-ended clock output C3. Complementary to QC2 when configured as
inverted output. 3.3V LVCMOS/LVTTL output levels.
Single-ended clock output C2. 3.3V LVCMOS/LVTTL output levels.
Single-ended clock output C1. Complementary to QC0 when configured as
inverted output. 3.3V LVCMOS/LVTTL output levels.
Single-ended clock output C0. 3.3V LVCMOS/LVTTL output levels.
Test mode control input. Compatible with LVCMOS/LVTTL (3.3V) signals.
See Table 3C for function.
PLL Bypass control input. Compatible with LVCMOS/LVTTL (3.3V) signals.
See Table 3B for function.
Supply voltage for the internal PLL (3.3V)
PLL lock detect output. 3.3V LVCMOS/LVTTL output levels.
Inverting differential clock input. Inverting input is biased to VDD / 2 by
default when left floating. Compatible with LVPECL and LVDS signals.
Non-inverting differential input clock. Compatible with LVPECL and LVDS
signals.
Core voltage for the reference clock (input) circuits (3.3V)
Alternative clock input. Compatible with LVCMOS/LVTTL (3.3V) signals.
PLL reference select control input. Compatible with LVCMOS/LVTTL (3.3V)
signals.See Table 3A for function.
Exposed pad of package. Connect to GND.
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
4
REVISION 1 02/25/15

4페이지










8V44N4614 전자부품, 판매, 대치품
8V44N4614 DATA SHEET
LVCMOS Output Phase
Outputs of the 8V44N4614 can invert the output phase, forming a
differential output with the neighboring LVCMOS output. Example
Table 3G. LVCMOS Output Phase Inversion
INVn
Output operation LVCMOS outputs
0 (default) Normal
1 Inverted
configuration to form differential LVCMOS outputs: Set to logic 1
(inverted): INVA4, INVB1, INVB3, INVC1 and INVC3:
• QA4 (co-located to QA3). Differential LVCMOS pair: QA3, QA4
• QB1 (co-located to QB0). Differential LVCMOS pair: QB0, QB1
• QB3 (co-located to QB2). Differential LVCMOS pair: QB2, QB3
• QC1 (co-located to QC0). Differential LVCMOS pair: QC0, QC1
• QC3 (co-located to QC2). Differential LVCMOS pair: QC2, QC3
When configured as differential LVCMOS, the outputs will generate
less noise (better cycle-to-cycle and period jitter). The differential
LVCMOS architecture of the device must be supported by equal line
length, loading and differential routing on the application board.
Configurable Output Levels
The three differential outputs of the QA bank can be individually
configured for LVDS and LVPECL levels (see Table 3H). Settings are
made through the SPI interface.
Table 3H. LEVn Output Level Function Table1
LEVn
0 (default)
Output Level
LVDS
1 LVPECL
1. n stands for a differential output of Bank A
Output Enable Operation
The device supports an enable/disable (high-impedance) function for
each individual output. The enable/disable state is pre-set by the
content of two SPI registers sets, ENA[12:0] and ENB[12:0]. Each set
contains 13 bits that is mapped 1:1 to the 13 outputs. A logic one in
these register bits correspond to the output enable state, logic 0 to
the output disable state. Two hardware pins (OENA and OENB)
control which of ENA, ENB register sets configure the outputs enable
state. For instance, if the hardware pins OENA = 1 and OENB = 0,
the device selects the 13 ENA bits for controlling the individual output
enable function; the ENB bits are ignored. By using the OENA and
OENB hardware pins, the user can switch between two
pre-configured output enable configuration sets, disable all outputs at
once perform a logic-OR function between the two register sets (see
Table 3I).
On power-up, the ENA and ENB register sets load default settings.
These default settings can be customized during final test of each
device using build-in one-time programmable cells.
After the first valid SPI write, the output enable state is controlled by
the SPI registers. Setting and changing the output enable state
through the SPI interface is asynchronous to the input reference
clock.
Table 3I. OENA, OENB Indirect Output Enable Control
OENA OENB Operation
0
0
All outputs are disabled regardless of the
ENA[12:0], ENB[12:0] register bit contents.
The output enable/disable state of each
0 1 output is defined by the corresponding bit in
the ENB[12:0] register set.
The output enable/disable state of each
output is defined by the corresponding bit in
1
0
the ENA[12:0] register set. OENA=1,
OENB=0 is the default configuration that is
loaded on power-up if OENA and OENB
are left open.
The output enable/disable state of each
output is defined by the result of the
logic-OR operation between the
1
1
corresponding bits of the ENA[12:0],
ENB[12:0] register sets. Example: the
output QA1 is enabled if either EAN[1] or
ENB[1] is set to logic 1, otherwise QA1 is
disabled.
Table 3J. Individual Output Enable Control1, 2
Bit
ENAn, ENBn Operation
LVDS: Output Qn, nQn is disabled
high-impedance state.
0
LVCMOS: Output Qn is disabled in
high-impedance state.
LVDS: Output Qn, nQn is enabled.
1
LVCMOS: Output Qn is enabled.
1. n stands for an individual output (QA[0:4], QB[0:3] and QC[0:3]).
The default / power-up state is one-time programmable.
2. See Table 3I for how the OENA, OENB inputs control the ENA
and ENB registers.
REVISION 1 02/25/15
7 FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER

7페이지


구       성 총 30 페이지수
다운로드[ 8V44N4614.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
8V44N4614

NG Jitter Attenuator and Clock Synthesizer

Integrated Device Technology
Integrated Device Technology

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵