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PDF 8T49N281 Data sheet ( Hoja de datos )
| Número de pieza | 8T49N281 | |
| Descripción | NG Octal Universal Frequency Translator | |
| Fabricantes | Integrated Device Technology | |
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FemtoClock® NG Octal Universal
Frequency Translator
8T49N281
DATA SHEET
General Description
The 8T49N281 has a fractional-feedback PLL that can be used as a
jitter attenuator or frequency translator. It is equipped with six integer
and two fractional output dividers, allowing the generation of up to 8
different output frequencies, ranging from 8kHz to 1GHz. Three of
these frequencies are completely independent of each other and the
inputs. The other five are related frequencies. The eight outputs may
select among LVPECL, LVDS or LVCMOS output levels.
This functionality makes it ideal to be used in any frequency
translation application, including 1G, 10G, 40G and 100G
Synchronous Ethernet, OTN, and SONET/SDH, including ITU-T
G.709 (2009) FEC rates. The device may also behave as a frequency
synthesizer.
The 8T49N281 accepts up to two differential or single-ended input
clocks and a crystal input. The PLL can lock to either input clock, but
both input clocks must be related in frequency.
The device supports hitless reference switching between input
clocks. The device monitors both input clocks for Loss of Signal
(LOS). It generates an alarm when an input clock failure is detected.
Automatic and manual hitless reference switching options are
supported. LOS behavior can be set to support gapped or un-gapped
clocks.
The 8T49N281 supports holdover with an initial accuracy of ±50ppB
from the point where the loss of all applicable input reference(s) has
been detected. It maintains a historical average operating point that
may be returned to in holdover at a limited phase slope.
The device places no constraints on input to output frequency
conversion, supporting all FEC rates, including the new revision of
ITU-T Recommendation G.709 (2009), most with 0ppm conversion
error.
The PLL has a register-selectable loop bandwidth from 0.5Hz to
512Hz.
Each output supports individual phase delay settings to allow
output-output alignment.
The device supports Output Enable inputs and Lock, Holdover and
LOS status outputs.
The device is programmable through an I2C interface. It also
supports I2C master capability to allow the register configuration to
be read from an external EEPROM.
Applications
• OTN or SONET / SDH equipment Line cards (up to OC-192, and
supporting FEC ratios)
• OTN de-mapping (Gapped Clock and DCO mode)
• Gigabit and Terabit IP switches / routers including support of
Synchronous Ethernet
• Wireless base station baseband
• Data communications
Features
• Supports SDH/SONET and Synchronous Ethernet clocks
including all FEC rate conversions
• Two differential outputs meet jitter limits for 100G Ethernet and
STM-256/OC-768
• <0.3ps RMS (including spurs): 12kHz to 20MHz
• All outputs <0.5ps RMS (including spurs) 12kHz to 20MHz
• Operating modes: locked to input signal, holdover and free-run
• Initial holdover accuracy of ±50ppb
• Accepts two LVPECL, LVDS, LVHSTL, HCSL or LVCMOS
input clocks
• Accepts frequencies ranging from 8kHz up to 875MHz
• Auto and manual input clock selection with hitless switching
• Clock input monitoring, including support for gapped clocks
• Phase-Slope Limiting and Fully Hitless Switching options to
control output phase transients
• Operates from a 10MHz to 40MHz fundamental-mode crystal
• Generates eight LVPECL /LVDS or sixteen LVCMOS output clocks
• Output frequencies ranging from 8kHz up to 1.0GHz (diff)
• Output frequencies ranging from 8kHz to 250MHz (LVCMOS)
• Four General Purpose I/O pins with optional support for status &
control:
• Four Output Enable control inputs may be mapped to any of the
eight outputs
• Lock, Holdover & Loss-of-Signal status outputs
• Open-drain Interrupt pin
• Programmable PLL bandwidth settings:
• 0.5Hz, 1Hz, 2Hz, 4Hz, 8Hz, 16Hz, 32Hz, 64Hz, 128Hz, 256Hz
or 512Hz
• Optional Fast Lock function
• Programmable output phase delays in steps as small as 16ps
• Register programmable through I2C or via external I2C EEPROM
• Bypass clock paths for system tests
• Power supply modes
VCC / VCCA / VCCO
3.3V / 3.3V / 3.3V
3.3V / 3.3V / 2.5V
3.3V / 3.3V / 1.8V (LVCMOS)
2.5V / 2.5V / 3.3V
2.5V / 2.5V / 2.5V
2.5V / 2.5V / 1.8V (LVCMOS)
• Power down modes support consumption as low as 1.5W (see
Section, “Power Dissipation and Thermal Considerations” for
details)
• -40°C to 85°C ambient operating temperature
• Package: 56QFN, lead-free RoHs (6)
8T49N281 REVISION 4 07/08/15
1 ©2015 Integrated Device Technology, Inc.
1 page  
8T49N281 DATA SHEET
Table 1. Pin Descriptions (Continued)
Number
Name
Type
Description
38
VCCO5
Power
35
VCCO6
Power
32
VCCO7
Power
53
52
CAP,
CAP_REF
Analog
18, Reserve
19
RESERVED
d
High-speed output supply voltage for output pair Q5, nQ5.
High-speed output supply voltage for output pair Q6, nQ6.
High-speed output supply voltage for output pair Q7, nQ7.
PLL External Capacitance.
Reserved pins.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics, VCC = VCCOX = 3.3V±5% or 2.5V±5%
Symbol
Parameter
Test Conditions
CIN
RPULLUP
Input Capacitance; NOTE 1
Internal
Pullup
Resistor
nRST,
SDATA , SCLK
nINT
GPIO[3:0]
RPULLDOWN
Internal Pulldown Resistor
LVCMOS
Q[0:1], Q[4:7]
VCCOX = 3.465V
LVCMOS Q[2:3]
VCCOX = 3.465V
Power
LVCMOS
Q[0:1], Q[4:7]
VCCOX = 2.625V
Dissipation LVCMOS Q[2:3]
VCCOX = 2.625V
CPD Capacitance LVCMOS
(per output Q[0:1], Q[4:7]
VCCOX = 1.89V
pair)
LVCMOS Q[2:3]
VCCOX = 1.89V
LVDS or LVPECL
Q[0:1], Q[4:7]
VCCOx = 3.465V or 2.625V
LVDS or LVPECL
Q[2:3]
VCCOx = 3.465V or 2.625V
ROUT
Output
Impedance
GPIO [3:0]
LVCMOS
Q[0:7], nQ[0:7]
Output HIGH
Output LOW
Minimum
NOTE: VCCOX denotes: VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7.
NOTE 1: This specification does not apply to OSCI and OSCO pins.
Typical
3.5
51
50
5.1
51
14.5
18.5
13
17.5
12.5
17
2
4.5
5.1
25
20
Maximum
Units
pF
k
k
k
k
pF
pF
pF
pF
pF
pF
pF
pF
k
REVISION 4 07/08/15
5 FEMTOCLOCK® NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR
5 Page 
8T49N281 DATA SHEET
Serial Control Port Description
Serial Control Port Configuration Description
The device has a serial control port capable of responding as a slave
in an I2C compatible configuration to allow access to any of the
internal registers for device programming or examination of internal
status. All registers are configured to have default values. See the
specifics for each register for details.
The device has the additional capability of becoming a master on the
I2C bus only for the purpose of reading its initial register
configurations from a serial EEPROM on the I2C bus. Writing of the
configuration to the serial EEPROM must be performed by another
device on the same I2C bus or pre-programmed into the device prior
to assembly.
I2C Mode Operation
The I2C interface is designed to fully support v1.2 of the I2C
Specification for Normal and Fast mode operations. The device acts
as a slave device on the I2C bus at 100kHz or 400kHz using the
address defined in the Serial Interface Control register (0006h), as
modified by the S_A0 input pin setting. The interface accepts
byte-oriented block write and block read operations. Two address
bytes specify the register address of the byte position of the first
register to write or read. Data bytes (registers) are accessed in
sequential order from the lowest to the highest byte (most significant
Current Read
bit first). Read and write block transfers can be stopped after any
complete byte transfer. During a write operation, data will not be
moved into the registers until the STOP bit is received, at which point,
all data received in the block write will be written simultaneously.
For full electrical I2C compliance, it is recommended to use external
pull-up resistors for SDATA and SCLK. The internal pull-up resistors
have a size of 51k typical.
S Dev Addr + R A Data 0 A Data 1 A
A Data n A P
Sequential Read
S
Dev Addr + W
A Offset Addr MSB A Offset Addr LSB A
Sr
Dev Addr + R
A
Data 0
A
Data 1
A
A Data n A P
Sequential Write
S Dev Addr + W A Offset Addr MSB A Offset Addr LSB A Data 0 A Data 1 A
A Data n A P
from master to slave
from slave to master
S = start
Sr = repeated start
A = acknowledge
A = none acknowledge
P = stop
Figure 3. I2C Slave Read and Write Cycle Sequencing
I2C Master Mode
When operating in I2C mode, the 8T49N281 has the capability to
become a bus master on the I2C bus for the purposes of reading its
configuration from an external I2C EEPROM. Only a block read cycle
will be supported.
As an I2C bus master, the 8T49N281 will support the following
functions:
• 7-bit addressing mode
• Base address register for EEPROM
• Validation of the read block via CCITT-8 CRC check against value
stored in last byte (E0h) of EEPROM
• Support for 100kHz and 400kHz operation with speed negotiation.
If bit d0 is set at Byte address 05h in the EEPROM, this will shift
from 100kHz operation to 400kHz operation.
• Support for 1- or 2-byte addressing mode
• Master arbitration with programmable number of retries
• Fixed-period cycle response timer to prevent permanently hanging
the I2C bus.
• Read will abort with an alarm (BOOTFAIL) if any of the following
conditions occur: Slave NACK, Arbitration Fail, Collision during
Address Phase, CRC failure, Slave Response time-out
The 8T49N281 will not support the following functions:
• I2C General Call
• Slave clock stretching
• I2C Start Byte protocol
• EEPROM Chaining
• CBUS compatibility
• Responding to its own slave address when acting as a master
• Writing to external I2C devices including the external EEPROM
used for booting
REVISION 4 07/08/15
11 FEMTOCLOCK® NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 8T49N281.PDF ] | |
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