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K4W2G1646C 데이터시트 PDF




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부품번호 K4W2G1646C 기능
기능 2Gb gDDR3 SDRAM C-die
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K4W2G1646C 데이터시트, 핀배열, 회로
Rev. 1.1, Sep. 2010
K4W2G1646C
2Gb gDDR3 SDRAM C-die
96FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
2010 Samsung Electronics Co., Ltd. All rights reserved.
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K4W2G1646C pdf, 반도체, 판매, 대치품
K4W2G1646C
datasheet
Rev. 1.1
gDDR3 SDRAM
15. Timing Parameters by Speed Grade .......................................................................................................................... 46
15.1 Jitter Notes ............................................................................................................................................................ 52
15.2 Timing Parameter Notes........................................................................................................................................ 53
15.3 Address/Command Setup, Hold and Derating : .................................................................................................... 54
15.4 Data Setup, Hold and Slew Rate Derating : .......................................................................................................... 61
16. Functional Description ................................................................................................................................................ 67
16.1 Simplified State Diagram ....................................................................................................................................... 67
16.2 Basic Functionality................................................................................................................................................. 68
16.3 RESET and Initialization Procedure ...................................................................................................................... 68
16.3.1. Power-up Initialization Sequence................................................................................................................... 68
16.3.2. Reset Initialization with Stable Power ............................................................................................................ 69
16.4 Register Definition ................................................................................................................................................. 70
16.4.1. Programming the Mode Registers ................................................................................................................. 70
16.4.2. Mode Register MR0 ....................................................................................................................................... 71
16.4.3. Burst Length, Type and Order........................................................................................................................ 71
16.4.4. CAS Latency .................................................................................................................................................. 72
16.4.5. Test Mode ...................................................................................................................................................... 72
16.4.6. DLL Reset ...................................................................................................................................................... 72
16.4.7. Write Recovery............................................................................................................................................... 72
16.4.8. Precharge PD DLL ......................................................................................................................................... 72
16.4.9. Mode Register MR1 ....................................................................................................................................... 73
16.4.10. DLL Enable/Disable ..................................................................................................................................... 74
16.4.11. Output Driver Impedance Control ................................................................................................................ 74
16.4.12. ODT Rtt Values ............................................................................................................................................ 74
16.4.13. Additive Latency (AL) ................................................................................................................................... 74
16.4.14. Write leveling................................................................................................................................................ 74
16.4.15. Output Disable ............................................................................................................................................. 74
16.4.16. TDQS, TDQS ............................................................................................................................................... 75
16.4.17. Mode Register MR2 ..................................................................................................................................... 76
16.4.18. Partial Array Self-Refresh (PASR) ............................................................................................................... 77
16.4.19. CAS Write Latency (CWL) ........................................................................................................................... 77
16.4.20. Auto Self-Refresh (ASR) and Self-Refresh Temperature (SRT) .................................................................. 77
16.4.21. Dynamic ODT (Rtt_WR)............................................................................................................................... 77
16.4.22. Mode Register MR3 ..................................................................................................................................... 77
16.4.23. Multi-Purpose Register (MPR) ..................................................................................................................... 77
17. gDDR3 SDRAM Command Description and Operation .............................................................................................. 78
17.1 Command Truth Table........................................................................................................................................... 78
17.2 Clock Enable (CKE) Truth Table ........................................................................................................................... 79
17.3 No OPeration (NOP) Command ............................................................................................................................ 79
17.4 Deselect Command ............................................................................................................................................... 79
17.5 DLL-off Mode......................................................................................................................................................... 80
17.6 DLL on/off switching procedure ............................................................................................................................. 81
17.6.1. DLL "on" to DLL "off" Procedure .................................................................................................................... 81
17.6.2. DLL "off" to DLL "on" Procedure .................................................................................................................... 82
17.7 Input clock frequency change................................................................................................................................ 83
17.8 Write Leveling........................................................................................................................................................ 84
17.8.1. DRAM setting for write leveling & DRAM termination function in that mode.................................................. 84
17.8.2. Procedure Description.................................................................................................................................... 85
17.8.3. Write Leveling Mode Exit ............................................................................................................................... 86
17.9 Extended Temperature Usage .............................................................................................................................. 87
17.9.1. Auto Self-Refresh mode - ASR Mode (optional) ............................................................................................ 87
17.9.2. Self-Refresh Temperature Range - SRT........................................................................................................ 87
17.10 Multi Purpose Register ........................................................................................................................................ 88
17.10.1. MPR Functional Description......................................................................................................................... 88
17.10.2. MPR Register Address Definition................................................................................................................. 89
17.10.3. Relevant Timing Parameters........................................................................................................................ 89
17.10.4. Protocol Example ......................................................................................................................................... 89
17.11 ACTIVE Command .............................................................................................................................................. 92
17.12 PRECHARGE Command .................................................................................................................................... 92
17.13 READ Operation.................................................................................................................................................. 92
17.13.1. READ Burst Operation ................................................................................................................................. 92
17.13.2. READ Timing Definitions.............................................................................................................................. 93
17.13.3. gDDR3 Clock to Data Strobe relationship.................................................................................................... 94
17.13.4. gDDR3 Data Strobe to Data relationship ..................................................................................................... 95
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K4W2G1646C 전자부품, 판매, 대치품
K4W2G1646C
datasheet
3. Package pinout/Mechanical Dimension & Addressing
3.1 x16 Package Pinout (Top view) : 96ball FBGA Package
Rev. 1.1
gDDR3 SDRAM
1
2
3 456 7
8
A
VDDQ
DQU5
DQU7
B VSSQ VDD
VSS
C
VDDQ
DQU3
DQU1
D
VSSQ
VDDQ
DMU
E
VSS
VSSQ
DQL0
F
VDDQ
DQL2
DQSL
G
VSSQ
DQL6
DQSL
H
VREFDQ
VDDQ
DQL4
J NC VSS RAS
K ODT VDD CAS
L NC CS WE
M VSS BA0 BA2
N VDD
A3
A0
P VSS
A5
A2
R VDD
A7
A9
T VSS RESET A13
DQU4
DQSU
DQSU
DQU0
DML
DQL1
VDD
DQL7
CK
CK
A10/AP
NC
A12/BC
A1
A11
NC
VDDQ
DQU6
DQU2
VSSQ
VSSQ
DQL3
VSS
DQL5
VSS
VDD
ZQ
VREFCA
BA1
A4
A6
A8
9
VSS
VSSQ
VDDQ
VDD
VDDQ
VSSQ
VSSQ
VDDQ
NC
CKE
NC
VSS
VDD
VSS
VDD
VSS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Ball Locations (x16)
Populated ball
Ball not populated
Top view
(See the balls through the package)
123456789
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
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부품번호상세설명 및 기능제조사
K4W2G1646C

2Gb gDDR3 SDRAM C-die

Samsung
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