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PDF LT3150 Data sheet ( Hoja de datos )
| Número de pieza | LT3150 | |
| Descripción | Very Low Dropout Linear Regulator Controller | |
| Fabricantes | Linear | |
| Logotipo |  |
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LT3150
Fast Transient Response,
Low Input Voltage, Very Low Dropout
Linear Regulator Controller
FEATURES
s Fast Transient Response Optimized with
Ceramic Output Capacitors
s FET RDS(ON) Defines Dropout Voltage
s ±1% Reference Tolerance Over Temperature
s Multifunction LDO Shutdown Pin with Latchoff
s Fixed Frequency 1.4MHz Boost Converter Generates
MOSFET Gate Drive
s Internally Compensated Boost Converter Uses Tiny
Capacitors and Inductor
s Independent Boost Converter Shutdown Control
Permits LDO Output Voltage Supply Sequencing
s 16-Lead SSOP Package
U
APPLICATIO S
s Microprocessor, ASIC and I/O Supplies
s Very Low Dropout Input-to-Output Conversion
s Logic Termination Supplies
, LTC and LT are registered trademarks of Linear Technology Corporation.
DESCRIPTIO
The LT®3150 drives a low cost external N-channel MOSFET
as a source follower to produce a fast transient response,
very low dropout voltage linear regulator. Selection of the
N-channel MOSFET RDS(ON) allows dropout voltages below
300mV for low VIN to low VOUT applications.
The LT3150 includes a fixed frequency boost regulator
that generates gate drive for the N-channel MOSFET. The
internally compensated current mode PWM architecture
combined with the 1.4MHz switching frequency permits
the use of tiny, low cost capacitors and inductors.
The LT3150’s transient load performance is optimized
with ceramic output capacitors. A precision 1.21V refer-
ence accommodates low voltage supplies.
Protection includes a high side current limit amplifier that
activates a fault timer circuit. A multifunction shutdown
pin provides either current limit time-out with latchoff,
overvoltage protection or thermal shutdown. Independent
shutdown control of the boost converter provides on/off
and sequencing control of the LDO output voltage.
TYPICAL APPLICATIO
1.8V to 1.5V, 4A Very Low Dropout Linear Regulator
(Typical Dropout Voltage = 65mV at IOUT = 4A)
MBR0520L
+ C1
6.19k
4.7µF 1%
1.37k
1%
LT3150
VIN2
FB1
SHDN2
SW
VIN1
SHDN1
SWGND
GND
GND
IPOS
INEG
GATE
FB2
COMP
6800pF
L1
10µH
5.1Ω
1.5k
50pF
CIN: PANASONIC SP SERIES EEFUE0E221R 20%
C1: AVX TAJA475M020R 20V 20%
L1: MURATA LQH32CN100K11 OR SUMIDA CDRH3D16100
+
Si4410
243Ω
1%
1020Ω
1%
CIN
220µF
2.5V
×2
VIN
1.8V
VOUT
1.5V
4A
2.2µF ×10
X5R CERAMIC
0805 CASE
3150 TA01
50mV/DIV
2A/DIV
Transient Response for
0.1A to 4A Output Load Step
20µs/DIV
3150 TA02
3150f
1
1 page  
LT3150
TYPICAL PERFOR A CE CHARACTERISTICS Linear Regulator Controller
FB2 Line Regulation
vs Temperature
0.030
0.025
0.020
0.015
0.010
0.005
0
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3150 G09
Gate Output Swing Low
vs Temperature
3.00
ILOAD = 50mA
2.75
2.50
NO LOAD
2.25
2.00
1.75
1.50
1.25
1.00
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3150 G12
Current Limit Threshold Voltage
vs Temperature
65
60
55 IPOS = 5V
IPOS = 3V
50
IPOS = 20V
45
40
35
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3150 G15
Error Amplifier Large-Signal
Voltage Gain vs Temperature
120
115
110
105
100
95
90
85
80
75
70
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3150 G10
Gate Output Swing High (VIN2 –
VGATE) vs Temperature
3.0
2.5
2.0
ILOAD = 50mA
1.5
1.0
NO LOAD
0.5
0
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3150 G13
Current Limit Threshold Voltage
Line Regulation vs Temperature
0
– 0.1
– 0.2
– 0.3
– 0.4
– 0.5
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3150 G16
Gain and Phase vs Frequency
200
150
PHASE
100
GAIN
50
0
1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
3150 G11
IPOS + INEG Supply Current
vs Temperature
1000
900
800 IPOS = INEG = 5V
IPOS = INEG = 12V
700 IPOS = INEG = 20V
600 IPOS = INEG = 3V
500
400
300
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3150 G14
SHDN2 Sink Current
vs Temperature
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3150 G17
3150f
5
5 Page 
LT3150
APPLICATIO S I FOR ATIO
solutions for microprocessor power supplies. This signifi-
cant performance benefit is what permits the elimination
of all bulk output capacitance.
Several other unique features are included in the design
that increase its functionality and robustness. These func-
tions comprise the remainder of the Block Diagram.
A high side sense, current limit amplifier provides active
current limiting for the regulator. The current limit ampli-
fier uses an external low value shunt resistor connected in
series with the external MOSFET’s drain. This resistor can
be a discrete shunt resistor or can be manufactured from
a Kelvin-sensed section of “free” PC board trace. All load
current flows through the MOSFET drain and thus, through
the sense resistor. The advantage of using high side
current sensing in this topology is that the MOSFET’s gain
and the main feedback loop’s gain remain unaffected. The
sense resistor develops a voltage equal to IOUT(RSENSE).
The current limit amplifier’s 50mV threshold voltage is a
good compromise between power dissipation in the sense
resistor, dropout voltage impact and noise immunity.
Current limit activates when the sense resistor voltage
equals the 50mV threshold.
Two events occur when current limit activates: the first is
that the current limit amplifier drives Q5 in the Block
Diagram and clamps the positive swing of the COMP node
in the main error amplifier to a voltage that provides an
output load current of 50mV/RSENSE. This action contin-
ues as long as the output current overload persists. The
second event is that a timer circuit activates at the SHDN2
pin. This pin is normally held low by a 5µA active pull-down
that limits to ≈ 100mV above ground. When current limit
activates, the 5µA pull-down turns off and a 15µA pull-up
current source turns on. Placing a capacitor in series with
the SHDN2 pin to ground generates a programmable time
ramp voltage.
The SHDN2 pin is also the positive input of COMP1. The
negative input is tied to the internal 1.21V reference.
When the SHDN2 pin ramps above VREF, the comparator
drives Q7 and Q8. This action pulls the COMP and GATE
pins low and latches the external MOSFET drive off. This
condition reduces the MOSFET power dissipation to zero.
The time period until the latched-off condition occurs is
typically equal to CSHDN2(1.11V)/15µA. For example, a
1µF capacitor on the SHDN2 pin yields a 74ms ramp time.
In short, this unique circuit block performs a current limit
time-out function that latches off the regulator drive after
a predefined time period. The time-out period selected is
a function of system requirements including start-up and
safe operating area. The SHDN2 pin is internally clamped
to typically 1.85V by Q9 and R10. The comparator tied to
the SHDN2 pin has 100mV of typical hysteresis to provide
noise immunity. The hysteresis is especially useful when
using the SHDN2 pin for thermal shutdown.
Restoring normal operation after the load current fault is
cleared is accomplished in two ways. One option is to
recycle the VIN2 LT3150 supply voltage as long as an
external bleed path for the SHDN2 pin capacitor is pro-
vided. The second option is to provide an active reset
circuit that pulls the SHDN2 pin below VREF. Pulling the
SHDN2 pin below VREF turns off the 15µA pull-up current
source and reactivates the 5µA pull-down. If the SHDN2
pin is held below VREF during a fault condition, the regu-
lator continues to operate in current limit into a short. This
action requires being able to sink 15µA from the SHDN2
pin at less than 1V. The 5µA pull-down current source and
the 15µA pull-up current source are designed low enough
in value so that an external resistor divider network can
drive the SHDN2 pin to provide overvoltage protection or
to provide thermal shutdown with the use of a thermistor
in the divider network. Diode-ORing these functions to-
gether is simple to accomplish and provides multiple
functionality for one pin.
If the current limit amplifier is not used, two choices
present themselves. The simplest choice is to tie the INEG
pin directly to the IPOS pin. This action defeats current limit
and provides the simplest, no frills circuit. Applications in
which the current limit amplifier is not used are where
extremely low dropout voltages must be achieved and the
50mV threshold voltage cannot be tolerated.
However, a second available choice permits a user to pro-
vide short-circuit protection with no external sensing. This
technique is activated by grounding the INEG pin. This action
disables the current limit amplifier because Schottky diode
D1 clamps the amplifier’s output and prevents Q5 from
pulling down the COMP node. In addition, Schottky diode
D2 turns off pull-down transistor Q4. Q4 is normally on and
3150f
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet LT3150.PDF ] | |
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