4015B PDF 데이터시트 검색

CD4015BMS December 1992 CMOS Dual 4-Stage Static Shift Register With Serial Input, Parallel Output Pinout CD4015BMS TOP VIEW CLOCK B 1 Q4B 2 Q3A 3 Q2A 4 Q1A 5 RESET A 6 DATA A 7 VSS 8 16 VDD 15 DATA B 14 RESET B 13 Q1B 12 Q2B 11 Q3B 10 Q4A 9 CLOCK A Features High-Voltage Type (20V Rating) Medium Speed Operation 12MH- (typ.) Clock Rate at VDD - VSS = 10V Fully Static Operation 8 Master-Slave Flip-Flops Plus Input and Output Buffering 100% Tested For Quiescent Current at 20V 5V, 10V and 15