48LC8M8A2 PDF 데이터시트 검색

64Mb: x4, x8, x16 SDRAM SYNCHRONOUS DRAM FEATURES PC66-, PC100-, and PC133-compliant Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access, precharge Programmable burst lengths: 1, 2, 4, 8, or full page Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes Self Refresh Modes: standard and low power 64ms, 4,096-cycle refresh LVTTL