89C51CC01 PDF 데이터시트 검색

Features 80C51 Core Architecture 256 Bytes of On-chip RAM 1K Bytes of On-chip ERAM 32K Bytes of On-chip Flash Memory Data Retention: 10 Years at 85°C Read, Write Cycle: 10K 2K Bytes of On-chip Flash for Bootloader 2K Bytes of On-chip EEPROM Read, Write Cycle: 100K 14-sources 4-level Interrupts Three 16-bit Timers, Counters Full Duplex UART Compatible 80C51 Maximum Crystal Frequency 40 MH- In X2 Mode, 20 MH- (CPU Core, 40 MHz) Five Ports: 32 + 2 Digital I, O Lines Five-channel 16