FIN1002 PDF 데이터시트 검색

FIN1002 LVDS 1-Bit High Speed Differential Receiver February 2002 Revised February 2002 FIN1002 LVDS 1-Bit High Speed Differential Receiver General Description This single receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is id