M2S56D20AKT PDF 데이터시트 검색

DDR SDRAM (Rev.1.0) Jul. '01 Preliminary M2S56D20, 30, 40AKT MITSUBISHI LSIs 256M Double Data Rate Synchronous DRAM PRELIMINARY Some of contents are subject to change without notice. DESCRIPTION M2S56D20AKT is a 4-bank x 16,777,216-word x 4-bit, M2S56D30AKT is a 4-bank x 8,388,608-word x 8-bit, M2S56D40AKT is a 4-bank x 4,194,304-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is