M2V56D20TP-75 PDF 데이터시트 검색

DDR SDRAM (Rev.0.0) Sep.'99 Preliminary MITSUBISHI LSIs M2S56D20, 30 TP 256M Double Data Rate Synchronous DRAM PRELIMINARY Some of contents are subject to change without notice. DESCRIPTION M2S56D20TP is a 4-bank x 16777216-word x 4-bit, M2S56D30TP is a 4-bank x 8388608-word x 8-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output data and dat