MT8941 PDF 데이터시트 검색

® CMOS ST-BUS™ FAMILY MT8941 Advanced T1, CEPT Digital Trunk PLL Features Provides T1 clock at 1.544 MH- locked to an 8 kH- reference clock (frame pulse) Provides CEPT clock at 2.048 MH- and STBUS clock and timing signals locked to an internal or external 8 kH- reference clock Typical inherent output jitter (unfiltered)= 0.07 UI peak-to-peak Typical jitter attenuation at: 10 Hz=23 dB,100 Hz=43 dB, 5 to 40 kH- ≥ 64 dB Jitter-free “FREE-RUN” mode Uncommitted two-input NAND gate Low po