PSD813F1 PDF 데이터시트 검색

PSD813F1 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V FEATURES SUMMARY s DUAL BANK FLASH MEMORIES 1 Mbit of Primary Flash Memory (8 Uniform Sectors) 256 Kbit Secondary EEPROM (4 Uniform Sectors) Concurrent operation: read from one memory while erasing and writing the other s 16 Kbit SRAM (BATTERY-BACKED) s PLD WITH MACROCELLS Over 3,000 Gates Of PLD: DPLD and CPLD DPLD - User-defined Internal chip-select decoding CPLD with 16 Output Macrocells (OMCs) and 24 Input Macr