QS5LV919133Q PDF 데이터시트 검색

QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER FEATURES: DESCRIPTION: QS5LV919 3.3V operation JEDEC compatible LVTTL level outputs Clock inputs are 5V tolerant < 300ps output skew, Q0 Q4 2xQ output, Q outputs, Q output, Q, 2 output Outputs 3-state and reset while OE, RST low PLL disable feature for low frequency testing Internal loop filter RC network Function