R5F117BC PDF 데이터시트 검색

RL78, I1D RENESAS MCU 1. OUTLINE 1.1 Features Ultra-low power consumption technology VDD = 1.6 V to 3.6 V HALT mode STOP mode SNOOZE mode RL78 CPU core CISC architecture with 3-stage pipeline Minimum instruction execution time: Can be changed from high speed (0.04167 s: @ 24 MH- operation with high-speed on-chip oscillator) to ultra-low speed (66.6 s: @ 15 kH- operation with low-speed on-chip oscillator clock) Multiply, divide, multiply & accumulate instructions are supported. Address