RD48FXXXX PDF 데이터시트 검색

m o .c UStrataFlash Wireless Memory Intel 4 t e System (LV18, LV30 SCSP) e h768-Mbit LVQ Family with Asynchronous Static RAM S a t Datasheet a .D Product Features w w w m o .c U 4 t e e h S a t a .D w w w ■ ■ ■ ■ ■ Device Architecture Code and data segment: 128- and 256Mbit density; PSRAM: 32- and 64-Mbit density; SRAM: 8 Mbit density. Top or bottom parameter configuration. Asymmetrical blocking structure. 16-KWord parameter blocks (Top or Bottom); 64-K Word main blocks. Zero-la