RGR1551 PDF 데이터시트 검색

Fiber Optic “Light to Logic” Receiver with Clock Recovery Preliminary Technical Data RGR1551 Features Light to Logic 20-Pin DIP Receiver Offers ECL Compatibility Long Reach, High Performance Sensitivity: 36 dBm Phase-Locked Loop (PLL) Timing Recovery Circuit Meets SONET Jitter Tolerance Requirements (CCITT G.958) Single +5 V Supply, Typically <700 mW SONET OC3 and SDH STM1 Compatible Multisourced Applications Telecommunication Networks SONET OC3 and SDH STM1 Compatible Local a