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Número de pieza | APW8706 | |
Descripción | High-Current DrMOS Power Module | |
Fabricantes | ANPEC | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de APW8706 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
No Preview Available ! APW8703/6/7
High-Performance, High-Current DrMOS Power Module
Features
• 4.5V ~ 5.5V Input Range for VCC & PVCC
• 4.5V ~ 25V Input Range for VIN
• Power-On-Reset Monitoring on VCC Pin
• APW8703-Up to 10A (peak), 8A (continuous) output
current scale
• APW8706-Up to 8A (peak), 6A (continuous) output
current scale
• APW8707-Up to 25A (peak), 13A (continuous)
output current scale
• Adjustable Over-Current Protection Threshold
• Up to 1.5MHz PWM operation
• Built-in Tri-State PWM input Function
• Built in EN Timing Control function
• Build in N-CH MOSFET for high side, N-CH MOSFET
for low side
• Skip Mode Operation
• Over-Temperature Protection
• TQFN 4x4-23P package and TQFN 5x5-30
packages
• Lead Free and Green Devices Available (RoHS
Compliant)
General Description
The APW8703/6/7 integrates a high-side N-channel
MOSFET and a low-side N-channel MOSFET with adap-
tive dead-time control. The APW8703/6/7 have a built-in
tri-state PWM input function which can support a number
of PWM controllers. When the PWM input signal stays tri-
state, the tri-state function shuts off the high-side MOSFET
and turns on the low-side MOSFET without consider ZC
function. The device is also equipped with Power-On-
Reset(POR) and enable control functions into a single
package and accurate current limit. The device over-cur-
rent protection monitors the output current by using the
voltage drop across the RDS(ON) of low-side MOSFET, elimi-
nating the need for a current sensing resistor that fea-
tures high efficiency and low cost. The POR circuit with
hysteresis monitors VCC supply voltage to start up/shut-
down the IC at power-on/off. The APW8703/6/7 also can
be enabled or disabled by other power system. Pulling
the EN pin high or low will turn on or shut off the device.
Applications
• Desktops
• Graphics Cards
• Severs
• Portable/Notebook Regulators
Simplified Application Circuit
VCC
C VCC
1uF
VCC
PWM
CONTROLLER
VCC
PVCC
APW8703
APW8706
APW8707
PWM
EN
VIN
LX
AGND
PGND
VIN
CIN
L VOUT
COUT
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright © ANPEC Electronics Corp.
Rev. A.2 - Jan, 2016
1
www.anpec.com.tw
1 page APW8703/6/7
Electrical Characteristics
Unless otherwise specified, these specifications apply over VDD=5V. Typical values are at TA=25oC.
Parame ter
Test Conditions
APW8 703/6/7
Min Typ Ma x
EN INPUT AND SMO D Input
EN/SMOD Input Logic High
2.0 - -
EN/SMOD Input Logic Low
- - 0 .8
EN/SMOD Input Cu rrent
V EN = 5V or VSMOD=5 V
GATE DRIVE R TIM INGS (re fer t o Figure 1 and Table 1 )
-1 - 1
tPDLU
tPDL L
tPD HU
tPDHL
PW M to Hig h sid e Gate
PW M to Low sid e Gate
LS to HS Gate Deadtime
HS to LS Gate Deadtime
PW M H to L to GH H to L (Note4 )
PW M L to H to GL H to L (Note4 )
G L H to L to GH L to H (No te 4)
G H H to L to GL L to H (No te 4)
-
-
-
-
18 -
25 -
20 -
20 -
Note4: Not tested in production.
Unit
V
V
uA
ns
ns
ns
ns
Copyright © ANPEC Electronics Corp.
Rev. A.2 - Jan, 2016
5
www.anpec.com.tw
5 Page APW8703/6/7
Layout Consideration
For all switching power supplies, the layout is an impor-
tant step in the design; especially at high peak currents
and switching frequencies. If the layout is not carefully
done, the regulator might show noise problems and duty
cycle jitter.
1. The input capacitors should be placed close to the VIN
pin, and the ground terminals of input capacitors and
output capacitors should be close PGND pin.
2. To minimize copper trace connections that can inject
noise into the system, the inductor should be placed as
close as possible to the LX pin to minimize the noise
coupling into other circuits.
3. The traces of PWM signal from the PWM controller to
the PWM pin of APW8703/6/7 should be short to elimi-
nate the parasitical capacitance; the parasitical capaci-
tance will cause an invalid PWM signal.
Copyright © ANPEC Electronics Corp.
Rev. A.2 - Jan, 2016
11
www.anpec.com.tw
11 Page |
Páginas | Total 18 Páginas | |
PDF Descargar | [ Datasheet APW8706.PDF ] |
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