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PDF MAX5719 Data sheet ( Hoja de datos )

Número de pieza MAX5719
Descripción 16 and 20-Bit Voltage DACs
Fabricantes Maxim Integrated 
Logotipo Maxim Integrated Logotipo



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MAX5717/MAX5719
EVALUATION KIT AVAILABLE
16 and 20-Bit Voltage DACs
General Description
The MAX5717 and MAX5719 are serial-input, unbuffered
16 and 20-bit voltage-output unipolar digital-to-analog
converters (DACs) with integrated feedback resistors
that allow bipolar operation when used with an external
operational amplifier. These DACs provide low glitch
energy, low noise, tight bipolar resistor matching, and high
accuracy. The DACs feature ±4LSB INL (max, 16-bit) over
the temperature range of -40°C to +105°C. Integrated
precision setting resistors make the DACs easy to use.
The MAX5717 and MAX5719 feature a 50MHz, 3-wire
SPI™, QSPI™, MICROWIRE™, and DSP-compatible
serial interface.
On power-up, the output resets to zero-scale, providing
additional safety for applications which drive valves or
other transducers that need to be off on power-up. The
DAC output settles in 750ns and has a low offset and
gain drift of ±0.1 ppm/°C of FSR.
The MAX5717 is functionally similar to the MAX542,
but with significantly faster settling time. The MAX5719
provides a similar speed improvement as well as an
increase in resolution to 20 bits.
Applications
● Test and Measurement Equipment
● Automatic Test Equipment
● Gain and Offset Adjustment
● Data-Acquisition Systems
● Process Control and Servo Loops
● Portable Instrumentation
● Programmable Voltage and Current sources
● Automatic Tuning
● Communication Systems
Benefits and Features
● 16 and 20-bit resolution
● ±4 LSB INL (Max, 16-bit)
● ±0.5 LSB DNL (Max, 16-bit)
● 750ns settling time (typ)
● 0.05 nV-sec glitch energy
6 nv/√Hz Output Noise Density
● Integrated ±0.025% (max) Bipolar Setting Resistors
● 4.5V to 5.5V Supply Range
● 4.0V to VDD Reference Input Range
● Safe Power-Up Reset-to-Zero-Scale DAC Output
(Unipolar)
● 50MHz 3-Wire SPI Interface
● -40°C to +105°C Operating Temperature Range.
● SO-14 Package
Simplified Block Diagram
REFF
REFS
VDD
MAX5717/
MAX5719
RINV
RFB
16-/20-BIT DAC
CS
LDAC
SCLK
DIN
CONTROL
LOGIC
16-/20-BIT DATA LATCH
SERIAL INPUT REGISTER
DGND
RFB
INV
OUT
AGNDF
AGNDS
Ordering Information appears at end of data sheet.
19-8567; Rev 0; 6/16

1 page




MAX5719 pdf
MAX5717/MAX5719
Typical Operating Characteristics
VDD = 5V, VREF = 4.096V, TA = 25°C unless otherwise noted.
16 and 20-Bit Voltage DACs
SUPPLY CURRENT
vs. TEMPERATURE
0.8 toc1
0.7
0.6
0.5
0.4
-60 -40 -20 0 20 40 60
TEMPERATURE (°C)
80 100 120
ZERO-CODE OFFSET ERROR
vs. TEMPERATURE (MAX5719)
1.2 toc3b
0.9
0.6
0.3
0
-60 -40 -20 0 20 40 60
TEMPERATURE (°C)
80 100 120
DNL vs. TEMPERATURE
(MAX5717)
0.4 toc5a
MAX DNL (LSB)
MIN DNL (LSB)
0.2
0.0
-0.2
-0.4
-60 -40 -20 0 20 40 60 80 100 120
TEMPERATURE (oC)
SUPPLY CURRENT
vs. REFERENCE VOLTAGE
0.8 toc2
0.7
0.6
0.5
0.4
4
4.2 4.4 4.6 4.8
REFERENCE VOLTAGE (V)
5
INL vs. TEMPERATURE
(MAX5717)
2.0
MAX INL (LSB)
1.5
MIN INL (LSB)
1.0
toc4a
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-60 -40 -20 0 20 40 60
TEMPERATURE (oC)
80 100 120
DNL vs. TEMPERATURE
(MAX5719)
2.0 toc5b
MAX DNL (LSB)
1.5
MIN DNL (LSB)
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-60 -40 -20 0 20 40 60 80 100 120
TEMPERATURE (oC)
ZERO-CODE OFFSET ERROR
vs. TEMPERATURE (MAX5717)
0.1 toc3a
0.05
0
-0.05
-0.1
-60 -40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
INL vs. TEMPERATURE
(MAX5719)
15.0
MAX INL (LSB)
toc4b
10.0 MIN INL (LSB)
5.0
0.0
-5.0
-10.0
-15.0
-60 -40 -20 0 20 40 60 80 100 120
TEMPERATURE (oC)
GAIN ERROR
vs. TEMPERATURE (MAX5717)
0.2 toc6a
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
-60 -40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
www.maximintegrated.com
Maxim Integrated 5

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MAX5719 arduino
MAX5717/MAX5719
16 and 20-Bit Voltage DACs
When the falling-edge of LDAC occurs after the digital
latency period, the DAC output begins to change on the
falling-edge of LDAC. When the falling-edge of LDAC
occurs before the end of the digital latency period, the
DAC output begins to change at the end of the digital
latency period. Settling time is approximately 750ns,
which means that the DAC will settle to value (N - 1) at
some point during the digital latency period for data (N).
The DAC will begin to settle to value (N) on either the next
falling-edge of LDAC (if LDAC goes low after the end of
the digital latency period) or at the end of the next digital
latency period (if LDAC goes low before the end of the
digital latency period).
Power-On Reset
The internal power-on reset circuit sets the DAC’s output
to 0V in unipolar mode and -VREF in bipolar mode when
VDD is first applied. This ensures that unexpected DAC
output voltages will not occur immediately following a
system power-up, such as after a loss of power.
Applications Information
Reference And Analog Ground Inputs
Apply an external voltage reference between the 4.0V
and VDD to the reference inputs. The reference voltage
determines the DAC’s full-scale output voltage. Kelvin
connections are provided for optimum performance.
Since these converters are designed as inverted R-2R
voltage-mode DACs, the input resistance seen by the
voltage reference is code-dependent. The worst-case
input resistance variation is from 2KΩ to 15KΩ. The
maximum change in load current for a 4.096V reference
is approximately 2mA. Therefore, when using a voltage
reference with 10ppm/mA load regulation, the reference
voltage may change by around 20ppm across the full
range of input codes. Therefore, a buffer amplifier should
be used when the best INL performance is needed. In
addition, the impedance of the path must be kept low
because it contributes directly to the load regulation error.
If separate force and sense lines are not used, tie the
appropriate force and sense pins together, close to the
package.
LOAD DATA N
MSB
DIN X D19 D18 D17
LSB
D0
X
X
LOAD DATA N+1
MSB
X D19 D18
SCLK
123
20 21
24
12
CS
20ns
LDAC
20ns
OUT
420ns
SETTLING TIME N-1
Figure 3. Throughput Timing (20-Bit Resolution Shown)
DIGITAL LATENCY: 1500ns max
20ns
20ns
SETTLING TIME N
www.maximintegrated.com
Maxim Integrated 11

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