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PDF CSS68HC68W1 Data sheet ( Hoja de datos )
| Número de pieza | CSS68HC68W1 | |
| Descripción | CMOS Serial Digital Pulse Width Modulator | |
| Fabricantes | CSS | |
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Custom Silicon Solutions, Inc.
CSS68HC68W1
April 2003
CMOS Serial Digital Pulse Width Modulator
Features
• Direct Replacement for Intersil CDP68HC68W1
• Programmable Frequency and Duty Cycle Output
• Serial Bus Input; Compatible with Motorola/Intersil SPI
Bus, Simple Shift-Register Type Interface
• 8 Lead PDIP Package
• Schmitt Trigger Clock Inputs
• 4V to 6V Operation, -40°C to 85°C Temperature Range
• 8 MHz Clock Input Frequency
Description
The CSS68HC68W1 modulates an input clock to provide
a variable frequency and variable duty-cycle output
signal. Three 8-bit registers (pulse width, frequency and
control) are accessed via a 3 line serial interface.
Pinout
(PDIP)
TOP VIEW
CLK 1
CS 2
VT 3
VSS 4
8 VDD
7 PWM
6 SCK
5 DATA
Block Diagram
CLK
INPUT CLK
MODULATOR
LOGIC
PWM
8 – STAGE RIPPLE
COUNTER
8 – STAGE
RIPPLE COUNTER
PULSE – WIDTH
DATA REGISTER
RESET
LOAD
LOAD
FREQUENCY
DATA REGISTER
DATA
SCK
CS
VT
8 – STAGE SHIFT
REGISTER
5 – STAGE
24 – STATE
COMPARATOR
8
16
24
VT
COMPARATOR
8 – STAGE SHIFT
REGISTER
CONTROL REGISTER
2 – STAGE SHIFT
LOAD
CAUTION: These devices are sensitive to electrostatic discharge; Follow proper IC Handling Procedures.
Custom Silicon Solutions, Inc. 17951 Sky Park Circle, Suite F, Irvine, CA 92614 Phone 949.797.9220 Fax 949.797.9225
All Rights Reserved.
1 page  
CSS68HC68W1
Introduction
The digital pulse width modulator (DPWM) divides down
a clock signal supplied via the CLK input as specified by
the control, frequency, and pulse width data registers.
The resultant output signal, with altered frequency and
duty cycle, appears at the output of the device on the
PWM pin.
Functional Pin Description
VDD and VSS
These pins are used to supply power and establish logic
levels within the PWM. VDD is a positive voltage with
respect to VSS (ground).
CLK
The CLK pin is an input only pin where the clock signal to
be altered by the PWM circuitry is supplied. This is the
source of the PWM output. This input frequency can be
internally divided by either one or two, depending on the
state of the CD bit in the control register.
CS
The CS pin is the chip select input to the PWM’s SPI
interface. A high-to-low (1 to 0) transition selects the
chip. A low-to-high (0 to 1) transition deselects the chip
and transfers data from the shift registers to the data
registers.
Functional Description
Serial Port
Data is entered into the three DPWM registers serially
through the DATA pin, accompanied by a clock signal
applied to the SCK. The user can supply these serial data
via shift register(s) or a microcontroller’s serial port, such
as the SPI port available on most CSS68HD05
microcontrollers. Microcontroller I/O lines can also be
used to simulate a serial port.
Data is written serially, most significant bit first, in 8, 16 or
24-bit increments. Data is sampled and shifted into the
PWMs shift register on each rising edge of the SCK. The
serial clock must be low when initiating a write cycle.
Therefore, when using a 68HC05 microcontroller’s SPI
port to provide data, program the microcontroller’s SPI
control register bit CPOL, CPHA to 0,0.
The CSS68HC68W1 latches data words after the device is
deselected. Therefore, CS must go high (inactive)
following each write to the W1.
Power-Up Initialization
Upon VDD power up, the output of the PWM chip will
remain at a low level (logic zero) until:
1. The chip is selected (CS pin pulled low).
2. 24-bits of information are shifted in.
3. The chip is deselected (CS pin pulled high).
VT
The VT pin is the input to the voltage threshold
comparator on the PWM. An analog voltage greater than
0.15*VDD on this pin will immediately cause the PWM
output to go to logic “0”. This will be the status until the
VT input is returned to a voltage below 0.1*VDD, the W1 is
selected, and then one or more of the data registers is
written to.
An analog voltage on this pin less than 0.5V (at VDD =
5V) will allow the device to operate as specified by the
values in the registers.
DATA
Data input at this pin is clocked into the shift register (i.e.,
latched) on the rising edge of the serial clock (SCK),
most significant bits first.
SCK
The SCK pin is the serial clock input to the PWM’s SPI
interface. A rising edge on this pin will shift data
available at the (DATA) pin into the shift register.
PWM
This pin provides the resultant output frequency and
pulse width. After VDD power up, the output on this pin
will remain a logic “0”, until the chip is selected, 24 bits of
information are clocked in, and the chip is deselected.
The 24-bits of necessary information pertain to the loading
of the PWM 8-bit registers, in the following order:
1. Control register
2. Frequency register
3. Pulse width register
See section entitled Pulse Width Modulator Data
Registers for a description of each register. Once
initialized, the specified PWM output signal will appear
until the device is reprogrammed or the voltage on the VT
pin rises above the specified threshold. Reprogramming
the device will update the PWM output after the end of the
present output clock period.
Reprogramming Shortcuts
After the device has been fully programmed upon power
up it is only necessary to input 8 bits of information to alter
the output pulse width, or 16 bits to alter the output
frequency.
Altering the Pulse Width: The pulse width may be
changed by selecting the chip, inputting 8 bits, and
deselecting the chip. By deselecting the chip, data from
the first 8-bit shift register are latched into the pulse width
register (PWM register). The frequency and control
registers remain unchanged. The updated PWM
information will appear at the output only after the end of
the previous total output period.
5
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