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PDF AD420 Data sheet ( Hoja de datos )
| Número de pieza | AD420 | |
| Descripción | Serial Input 16-Bit 4 mA-20 mA/ 0 mA-20 mA DAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
FEATURES
4 mA–20 mA, 0 mA–20 mA or 0 mA–24 mA
current output
16-bit resolution and monotonicity
±0.012% max integral nonlinearity
±0.05% max offset (trimmable)
±0.15% max total output error (trimmable)
Flexible serial digital interface (3.3 MBPS)
On-Chip loop fault detection
On-chip 5 V reference (25 ppm/°C max)
Asynchronous CLEAR function
Maximum power supply range of 32 V
Output loop compliance of 0 V to VCC − 2.75 V
24-Lead SOIC and PDIP packages
GENERAL DESCRIPTION
The AD420 is a complete digital to current loop output
converter, designed to meet the needs of the industrial control
market. It provides a high precision, fully integrated, low cost
single-chip solution for generating current loop signals in a
compact 24-lead SOIC or PDIP package.
The output current range can be programmed to 4 mA to
20 mA, 0 mA to 20 mA or to an overrange function of 0 mA to
24 mA. The AD420 can alternatively provide a voltage output
from a separate pin that can be configured to provide 0 V to 5 V,
0 V to 10 V, ±5 V, or ±10 V with the addition of a single external
buffer amplifier.
The 3.3 M Baud serial input logic design minimizes the cost of
galvanic isolation and allows for simple connection to commonly
used microprocessors. It can be used in 3-wire or asynchronous
mode and a serial-out pin is provided to allow daisy chaining of
multiple DACs on the current loop side of the isolation barrier.
The AD420 uses sigma-delta (Σ-Δ) DAC technology to achieve
16-bit monotonicity at very low cost. Full-scale settling to 0.1%
occurs within 3 ms. The only external components that are
required (in addition to normal transient protection circuitry)
are two low cost capacitors which are used in the DAC out-
put filter.
If the AD420 is used at extreme temperatures and supply
voltages, an external output transistor can be used to minimize
power dissipation on the chip via the BOOST pin. The FAULT
DETECT pin signals when an open circuit occurs in the loop.
The on-chip voltage reference can be used to supply a precision
+5 V to external components in addition to the AD420 or, if the
Rev. I
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
Serial Input 16-Bit
4 mA–20 mA, 0 mA–20 mA DAC
AD420
VLL
REF OUT
REF IN
DATA OUT
CLEAR
LATCH
CLOCK
DATA IN
RANGE
SELECT 1
RANGE
SELECT 2
FUNCTIONAL BLOCK DIAGRAM
VCC
REFERENCE
4kΩ
AD420
40Ω
BOOST
DATA I/P
REGISTER
CLOCK
16-BIT
DAC
SWITCHED
CURRENT
SOURCES
AND
FILTERING
1.25kΩ
IOUT
VOUT
FAULT
DETECT
OFFSET CAP 1 CAP 2
TRIM
Figure 1.
GND
user desires temperature stability exceeding 25 ppm/°C, an
external precision reference such as the AD586 can be used as
the reference. The AD420 is available in a 24-lead SOIC and
PDIP over the industrial temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1. The AD420 is a single chip solution for generating 4 mA to
20 mA or 0 mA to 20 mA signals at the controller end of
the current loop.
2. The AD420 is specified with a power supply range from
12 V to 32 V. Output loop compliance is 0 V to VCC − 2.75 V.
3. The flexible serial input can be used in 3-wire mode
with SPI® or MICROWIRE® microcontrollers, or in
asynchronous mode, which minimizes the number of
control signals required.
4. The serial data out pin can be used to daisy chain any
number of AD420s together in 3-wire mode.
5. At power-up, the AD420 initializes its output to the low
end of the selected range.
6. The AD420 has an asynchronous CLEAR pin, which sends
the output to the low end of the selected range (0 mA, 4 mA,
or 0 V).
7. The AD420 BOOST pin accommodates an external
transistor to off-load power dissipation from the chip.
8. The offset of ±0.05% and total output error of ±0.15% can
be trimmed if desired, using two external potentiometers.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VCC to GND
IOUT to GND
Digital Inputs to GND
Digital Output to GND
VLL and REF OUT: Outputs Safe for
Indefinite Short to Ground
Storage Temperature
Lead Temperature (Soldering, 10 sec)
Lead Temperature, Soldering Reflow
Thermal Impedance:
SOIC (R) Package
PDIP (N) Package
Rating
32 V
VCC
−0.5 V to +7 V
−0.5 V to VLL + 0.3 V
−65°C to +150°C
+300°C
+260°C
θJA = 75°C/W
θJA = 50°C/W
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
AD420
Table 3. Truth Table
Inputs
Range
CLEAR Select 2
0X
1X
Range
Select 1
X
X
X0
X0
X1
X1
0
1
0
1
ESD CAUTION
Operation
Normal operation
Output at bottom of
span
0 V–5 V range
4 mA–20 mA range
0 mA–20 mA range
0 mA–24 mA range
Rev. I | Page 5 of 16
5 Page 
Data Sheet
THREE-WIRE INTERFACE
Figure 9 shows the AD420 connected in the 3-wire interface
mode. The AD420 data input block contains a serial input shift
register and a parallel latch. The contents of the shift register
are controlled by the DATA IN signal and the rising edges of the
CLOCK. Upon request of the LATCH pin the DAC and internal
latch are updated from the shift register parallel outputs. The
CLOCK should remain inactive while the DAC is updated.
Refer to the timing requirements for 3-wire interface.
LATCH
CLOCK
DATA IN
FAULT DETECT
AD420
DAC1
FAULT
DETECT
VCC
LATCH
VCC
10kΩ
CLOCK
DATA
IN
GND
DATA
OUT
IOUT
RLOAD
VLL
AD420
DAC2
FAULT
DETECT
VCC
LATCH
VCC
CLOCK
DATA
IN
GND
DATA
OUT
IOUT
RLOAD
Figure 9. Three-Wire Interface Using Multiple DACs with Joint Fault Detect
USING MULTIPLE DACS WITH FAULT DETECT
The 3-wire interface mode can utilize the serial DATA OUT for
easy interface to multiple DACs. To program the two AD420s in
Figure 9, 32 data bits are required. The first 16 bits are clocked
into the input shift register of DAC1. The next 16 bits
transmitted pass the first 16 bits from the DATA OUT pin of
DAC1 to the input register of DAC2. The input shift registers of
the two DACs operate as a single 32-bit shift register, with the
leading 16 bits representing information for DAC2 and the
trailing 16 bits serving for DAC1. Each DAC is then updated
upon request of the LATCH pin. The daisy-chain can be
extended to as many DACs as required.
AD420
ASYNCHRONOUS INTERFACE USING
OPTOCOUPLERS
The AD420 connected in asynchronous interface mode with
optocouplers is shown in Figure 10. Asynchronous operation
minimizes the number of control signals required for isolation
of the digital system from the control loop. The resistor connected
between the LATCH pin and VCC is required to activate this
mode. For operation with VCC below 18 V use a 50 kΩ pull-up
resistor; from 18 V to 32 V, use 100 kΩ.
Asynchronous mode requires that the clock run at 16 times the
data bit rate, therefore, to operate at the maximum input data rate
of 150 kBPS, an input clock of 2.4 MHz is required. The actual
data rate achieved may be limited by the type of optocouplers
chosen. The number of control signals can be further reduced
by creating the appropriate clock signal on the current loop
side of the isolation barrier. If optocouplers with relatively slow
rise and fall times are used, Schmitt triggers may be required on
the digital inputs to prevent erroneous data being presented to
the DAC.
+24V
100kΩ
23 VCC AD420
7 LATCH
+5V 2 VLL
CLOCK
8 CLOCK
DATA
9 DATA IN
11 GND
GALVANIC
BARRIER
ISOLATION
Figure 10. Asynchronous Interface Using Optocouplers
Rev. I | Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD420.PDF ] | |
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