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PDF HSP50415 Data sheet ( Hoja de datos )
| Número de pieza | HSP50415 | |
| Descripción | Wideband Programmable Modulator (WPM) | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
HSP50415
March 2000 File Number 4559.5
Wideband Programmable Modulator
(WPM)
The HSP50415 Wideband Programmable Modulator (WPM)
is a quadrature amplitude modulator/upconverter designed
for wideband digital modulation. The WPM combines
shaping and interpolation filters, a complex modulator, timing
and carrier NCOs and dual DACs into a single package.
The HSP50415 supports vector modulation, accepting up to
16-bit In phase (I) and Quadrature (Q) samples to generate
virtually any quadrature AM or PM modulation format. A
constellation mapper and 24 Symbol span interpolation
shaping filter is provided for the input baseband signals. Gain
adjustment is provided after the shaping FIR filter. A timing
error generator in the input section allows the on-chip timing
NCO to track the input timing.
The WPM includes a Numerically Controlled Oscillator
(NCO) driven interpolation filter, which allows the input and
output sample rate to have a non-integer or variable
relationship. This re-sampling feature simplifies use of
sample rates that do not have harmonic or integer frequency
relationships to the input data rate and decouples the carrier
from the DATACLK.
A complex quadrature modulator modulates the baseband
data on a programmable carrier center frequency. The
WPM offers digital output spurious Free Dynamic Range
(SFDR) that exceeds 70dB at the maximum output sample
rate of 100MSPS, for input sample rates as high as
25MSPS. X/SIN(X) rolloff compensation filtering is
provided. Real 14-bit digital output data is available prior to
the 12-bit DACs providing 20mA full scale output current.
Block Diagram
Features
• Output Sample Rates . . . . . . . . . . . . . . . . . . to 100MSPS
• Input Data Rates . . . . . . . . . . . . . . . . Up to 25MSPS (I/Q)
• 32-Bit Programmable Carrier NCO
• X/SIN(X) Rolloff Compensation
• Programmable I and Q Shaping FIR Filters:
- Up to 24 Symbol Span
• Fixed or NCO Controlled Interpolation:
- Interpolation Range . . . . . . . . . . . . . . . . . . 4 to > 128K
- Digital PLL to Lock to Input Symbol Clock
• Digital Signal Processing Capable of >70dB SFDR
• Dual 12-bit D/A Processing Capable of >50 dB SFDR
Applications
• Wide-Band Digital Modulation
• Base Station Modulators
• HSP50415EVAL1 Evaluation Board Available
Ordering Information
PART
NUMBER
TEMP
RANGE (oC)
PACKAGE
PKG. NO
HSP50415VI
-40 to 85 100 Ld MQFP Q100.14x20
HSP50415EVAL1 Evaluation CCA, Development S/W, and User’s
Manual
W/R
CONTROL
µP
INTERFACE
DATA
DATACLK
DATA
I
INTERFACE/
FIFO
CONST
MAP
Q
CARRIER
NCO
COS
SIN
SHAPING/
INTERPOLATION
FILTERS
COMPLEX
MIXER
X
SIN(X)
SHAPING/
INTERPOLATION
FILTERS
X
SIN(X)
14
/
12-BIT
DAC
12-BIT
DAC
DIGITAL OUT
I OUT
Q OUT
2XSYMCLK
REFCLK
SYMBOL NCO/
DIGITAL PLL
CLK MULTIPLIER
ANALOG PLL
CLK
4-1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
1 page  
HSP50415
Pin Descriptions (Continued)
NAME
TYPE
DESCRIPTION
ICOMP1,
QCOMP1
I Compensation Pin for use in Reducing Bandwidth/Noise. Each pin should be individually decoupled to AVDD with
a 0.1µF capacitor. To minimize crosstalk, the part was designed so that these pins must be connected externally,
ideally directly under the device packaging. The voltage on these pins is used to drive the gates of the PMOS
devices that make up the current cells. Only the ICOMP1 pin is driven and therefore QCOMP1 needs to be
connected to ICOMP1, but de-coupled separately to minimize crosstalk.
ICOMP2,
QCOMP2
I Compensation Pin for Internal Bias Generation. Each pin should be individually decoupled to AGND with a 0.1µF
capacitor. The voltage generated at these pins represents the voltage used to supply 2.0V nominal power to the
switch drivers. This arrangement helps to minimize clock feedthrough to the current cell transistors for reduced
glitch energy and improved spectral performance.
REFLO
I Reference Low Select. When the internal reference is enabled, this pin serves as the precision ground reference
point for the internal voltage reference circuitry and therefore needs to have a good connection to analog ground
to enable internal 1.2V reference. To disable the internal reference circuitry this pin should be connected to AVDD.
REFIO
I Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is enabled. Use
0.1µF cap to ground when internal reference is enabled.
FSADJ
I Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output Current =
32 x VFSADJ/RSET. Where VFSADJ is the voltage at this pin. VFSADJ tracks the voltage on the REFIO pin; which
is typically 1.2V if the internal reference is used.
RESV
- Reserved. These pins must be floating (not connected) for proper operation.
NC - No Connection. Pins may be connected to GND, AGND, DGND or left floating.
Functional Description
The HSP50415 is a wideband programmable modulator that
accepts an input quadrature data stream at programmable
symbol rates of up to 25MSPS (QPSK) and outputs a
modulated quadrature data stream at the final sample rate
up to 100MHz. The allowable symbol rates depend on the
modulation type selected (QPSK, 16QAM, etc.). The input
data format is parallel with respect to the bits, but serial with
respect to the I and Q samples and may be input at a
constant symbol rate or burst in at a different rate. The
HSP50415 can symbol map the input data stream per a user
programmable look up table thus allowing any standard to
be supported. The mapped symbols are then interpolated to
the final sample rate and low-pass filtered in order to limit the
spectral occupancy of the signal. The first stage filter
coefficients are user programmable, with subsequent filter
stages having fixed coefficients. The HSP50415 then
modulates the symbol data at the final sample rate onto a
carrier signal that is tunable from 0.023Hz - 50MHz (for a
final sample rate of 100MHz) producing a quadrature signal.
The signal may then be optionally X/SIN(X) filtered to
compensate for the SIN(X)/X roll-off of the DACs. To correct
for system (or DAC induced) gain imbalances between the In
phase and Quadrature signals there is a final gain correction
stage prior to the output. The final Intermediate Frequency
(IF) digital output can be converted to differential analog
signals via the onboard 12-bit DACs or may be optionally
brought out as 14-bit digital data. The 100-pin MQFP
package provides a real digital output at 1/2 the final sample
rate.
System CLK Generation
The HSP50415 receives I and Q input data serially at twice
the input symbol rate. The data is converted to a parallel
quadrature data stream at the symbol rate by the Front End
Data Input Block. This data stream is upsampled to the final
output sample rate of the device (FSout). This output sample
rate (maximum rate of 100MHz) is used to clock the last
stage of the digital logic and the dual 12-bit DACs and may
be provided externally on the CLK pin or may be generated
by an internal analog PLL (APLL). When enabled, the APLL
uses the CLK pin as a reference and provides a selectable
CLK multiplier of x2, x4, x8, x16 or x32 or CLK divider of /2,
/4 or /8.
An external loop filter is required to be supplied at PLLRC.
The recommend configuration is shown in Figure 1, with
suggested component values calculated as:
User Input Terms:
APLLclkdivider=APLL CLK divider programmed input
APLLvcodivider=APLL VCO divider programmed input
Fclk=CLK frequency input
Fscale=loop bandwidth divisor input
Pm=loop phase margin input (degrees)
Component calculation formulas:
C1=(Fvcogain*Icp)/(wo*wo*sqrt(kk))
C2=kk*C1
R1=1/sqrt(Fvcogain*Icp*C1*sqrt(C2/C1))
Where:
Fvcogain=231000000/APLLvcodivider
Icp=0.000353
4-5
5 Page 
HSP50415
resulting 23-bit output rounded at bit position 5 (multOut<5>)
to 17-bits. The extra bit is carried to check for overflow at the
output of the shifter. The output of the multiplier
(multOut<22:6>) is then shifted to the appropriate position
per the exponent bits with a shift value of 0xB positioning the
data at the top of the shifter. The final shifted output is then
checked for saturation and limited to 16-bits before being
output.
Fixed Coefficient 19-TAP Interpolating
Halfband
Following the post-FIR gain stage is a pair of fixed coefficient
19-tap interpolate by 2 halfband filters. The halfband filter
may be totally bypassed if not required. If bypassed, the data
to the filter is zeroed which reduces power consumption. The
halfband filter coefficients are:
1, 0, -17, 0, 87, 0, -299, 0, 1252, 2048, 1252, 0, -299, 0, 87,
0, -17, 0, 1
The interpolate by 2 is accomplished via zero-stuffing and
low-pass filtering. The output of this filter is rounded to 16-
bits. The output is checked for saturation and limited if
necessary. The data exits the halfband filters as a parallel
I<15:0> and Q<15:0> data stream at the interpolated sample
rate. Figure 8 shows the frequency response of the Half-
Band filter.
100
80
60
40
20
0
-20
-40
-60
-80
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
NORMALIZED FREQUENCY (NYQUIST = 1)
FIGURE 8. HALF-BAND FREQUENCY RESPONSE
Interpolating Filter
Following the halfband stage, the data enters the last stage
of interpolating filters. Again, the I and Q filters are identical
so the subsequent discussion will refer to a single channel.
The data is input to the interpolating filter at this stage’s input
sample rate which is dependent on the previous stage’s
interpolation rate. At this stage the input sample rate clock is
generated by the SYMBOL NCO. For every output sample
generated, there is a 12-bit phase value that is also
generated in the SYMBOL NCO (the top 12-bits of the phase
accumulator). The Interpolator uses this phase value to
compute output samples at the output sample rate (FSOUT)
which is the final output sample rate of the chip. The nulls in
the interpolation filter frequency response align with the
interpolation images of the shaping filter. Input to this stage
should be no greater than -2dB fullscale to prevent overflow.
The impulse response of the Interpolation filter is shown in
Figures 9 through 11 for an interpolate by 16 filter (the
interpolation ratio, L, is equal to 16). This block may be
bypassed if desired. Figures 12 through 17 depict the
response for varying interpolation ratios.
4-11
11 Page | ||
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| PDF Descargar | [ Datasheet HSP50415.PDF ] | |
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