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PDF AX88796L Data sheet ( Hoja de datos )
| Número de pieza | AX88796L | |
| Descripción | 3-in-1 Local Bus Fast Ethernet Controller | |
| Fabricantes | ETC | |
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AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
10/100BASE 3-in-1 Local CPU Bus Fast Ethernet Controller
with Embedded SRAM
Document No.: AX796-17 / V1.7 / Jan. 25 ’02
Features
• Highly integrated with embedded 10/100Mbps
MAC, PHY and Transceiver
• Embedded 8K * 16 bit SRAM
• Compliant with IEEE 802.3/802.3u
100BASE-TX/FX specification
• NE2000 register level compatible instruction
• Single chip local CPU bus 10/100Mbps Fast
Ethernet MAC Controller
• Support both 8 bit and 16 bit local CPU interfaces
include MCS-51 series, 80186 series and MC68K
series CPU
• Support both 10Mbps and 100Mbps data rate
• Support both full-duplex or half-duplex operation
• Provides an extra MII port for supporting other
media. For example, Home LAN application
• Support EEPROM interface to store MAC address
• External and internal loop-back capability
• Support Standard Print Port for printer server
application
• Support upto 3/1 General Purpose In/Out pins
• 128-pin LQFP low profile package
• Low Power Consumption, typical under 100mA
• 0.25 Micron low power CMOS process. 25MHz
Operation, Pure 3.3V operation with 5V I/O
tolerance.
*IEEE is a registered trademark of the Institute of
Electrical and Electronic Engineers, Inc.
*All other trademarks and registered trademark are
the property of their respective holders.
Product description
The AX88796 Fast Ethernet Controller is a high performance and highly integrated local CPU bus Ethernet Controller
with embedded 10/100Mbps PHY/Transceiver and 8K*16 bit SRAM. The AX88796 supports both 8 bit and 16 bit local
CPU interfaces include MCS-51 series, 80186 series, MC68K series CPU and ISA bus. The AX88796 implements both
10Mbps and 100Mbps Ethernet function based on IEEE802.3 / IEEE802.3u LAN standard. The AX88796 also provides
an extra IEEE802.3u compliant media-independent interface (MII) to support other media applications. Using MII
interface, Home LAN PHY type media can be supported.
As well as, the chip also provides optional Standard Print Port ( parallel port interface ), can be used for printer server
device or treat as simple general I/O port. The chip also support upto 3/1 additional General Purpose In/Out pins
System Block Diagram
AD BUS
Addr L
Addr H
Ctl BUS
AX88796
With
10/100 Mbps
PHY/TxRx
Optional Print Port
Or General I/O Ports
Optional
Home LAN
PHY
RJ11
RJ45
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No liability
is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
First Released Date : July/31/2000
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500
FAX: 886-3-579-9558
http://www.asix.com.tw
1 page  
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
1.0 Introduction
1.1 General Description:
The AX88796 provides industrial standard NE2000 registers level compatible instruction set. Various drivers are easy
acquired, maintenance and usage. No much additional effort to be paid. Software is easily port to various embedded
systems with no pain and tears
The AX88796 Fast Ethernet Controller is a high performance and highly integrated local CPU bus Ethernet Controller
with embedded 10/100Mbps PHY/Transceiver and 8K*16 bit SRAM. The AX88796 supports both 8 bit and 16 bit local
CPU interfaces include MCS-51 series, 80186 series, MC68K series CPU and ISA bus. The AX88796 implements both
10Mbps and 100Mbps Ethernet function based on IEEE802.3 / IEEE802.3u LAN standard. The AX88796 also provides
an extra IEEE802.3u compliant media-independent interface (MII) to support other media applications. Using MII
interface, Home LAN PHY type media can be supported.
As well as, the chip also provides optional Standard Print Port ( parallel port interface ), can be used for printer server
device or treat as simple general I/O port. The chip also support upto 3/1 additional General Purpose In/Out pins
The main difference between AX88796 and AX88195 are : 1) Embedded packet buffer memory 2) Built-in 10/100Mbps
PHY/Transceiver 3) Replace memory I/F with PHY/Transceiver I/F. 4) Canceling SAX address decoding. 5) Fix
interrupt status can’t always clean up problem of AX88195. 6) Add upto 3/1 general Purpose In/Out pins.
AX88796 use 128-pin LQFP low profile package, 25MHz operation, and single 3.3V operation with 5V I/O tolerance.
The ultra low power consumption is an outstanding feature and enlarges the application field. It is suitable for some
power consumption sensitive product like small size embedded products, PDA (Personal Digital Assistant) and Palm
size computer …etc.
1.2 AX88796 Block Diagram:
EECS
EECK
EEDI
EEDO
Print Port
or
General
I/O
8K* 16 SRAM
and Memory Arbiter
SEEPROM
I/F
SPP
/ GPIO
NE2000
Registers
Remote
DMA
FIFOs
Host Interface
STA
MAC
Core
&
PHY+
Tranceiver
SMDC
SMDIO
TPI, TPO
MII I/F
Fig - 1 AX88796 Block Diagram
Ctl BUS
SA[9:0]
SD[15:0]
5 ASIX ELECTRONICS CORPORATION
5 Page 
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
1.3.4 AX88796 Pin Connection Diagram for MCS-51 Mode
GPI[0]/LINK
VDD
VSS
GPI[1]/DPX
TX_CLK
TX_EN
TXD[0]
TXD[1]
TXD[2]
TXD[3]
GPI[2]/SPD
VDD
VSS
I_OP
IO_BASE[0]
IO_BASE[1]
IO_BASE[2]
GPO[0]
NC
NC
NC
NC
NC
VDD
VSS
/CS
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
AX88796
Local CPU Bus
10/100BASE-TX
MAC Controller
(for 8051 Interface)
64 NC
63 VSS
62 I_ACT
61 I_SPEED
60 I_LINK
59 CPU[1]
58 CPU[0]
57 VDD
56 VDDA
55 VSSA
54 VSS
53 VDD
52 VSS
51 EECS
50 EECK
49 EEDI
48 EEDO
47 TEST2
46 IDDQ
45 BIST
44 CLKO25M
43 VSS
42 SD[0]
41 SD[1]
40 VDD
39 SD[2]
Fig - 7 AX88796 Pin Connection Diagram for MCS-51 Mode
11 ASIX ELECTRONICS CORPORATION
11 Page | ||
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