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PDF LMA2009JC45 Data sheet ( Hoja de datos )
| Número de pieza | LMA2009JC45 | |
| Descripción | 12 x 12-bit Multiplier-Accumulator | |
| Fabricantes | LOGIC Devices Incorporated | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LMA2009JC45 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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DEVICES INCORPORATED
DEVICES INCORPORATED
LMA 1009/2009
12 x 12-LbiMt MAult1ip0lie0r-A9c/c2um0u0la9tor
12 x 12-bit Multiplier-Accumulator
FEATURES
DESCRIPTION
u 20 ns Multiply-Accumulate Time
u Low Power CMOS Technology
u Replaces Fairchild TDC1009/
TMC2009
u Two’s Complement or Unsigned
Operands
u Accumulator Performs Preload,
Accumulate, and Subtract
u Three-State Outputs
u 68-pin PLCC, J-Lead
LMA1009/2009 BLOCK DIAGRAM
CLK A
CLK B
RND
TC
ACC
SUB
OEX
OEM
OEL
PREL
CLK R
PRELOAD
CONTROL
LOGIC
3
LEX
LEM
LEL
3
OEX
OEM
OEL
LEX
27
The LMA1009 and LMA2009 are high-
speed, low power 12-bit multiplier-accu-
mulators. They are pin-for-pin equiva-
lent to the TRW TDC1009/TMC2009
multiplier-accumulators. The LMA1009
and LMA2009 are functionally identical;
they differ only in packaging. Full ambi-
ent temperature range operation is
achieved by the use of advanced CMOS
technology.
The LMA1009/2009 produces the 24-bit
product of two 12-bit numbers. The
results of a series of multiplications may
be accumulated to form the sum of prod-
ucts. Accumulation is performed to
27-bit precision with the multiplier prod-
uct sign extended as appropriate.
A11-0
12
A REGISTER
B11-0
12
B REGISTER
24
R
R+A
R–A
A
PASS R
27
LEM
3
LEL
12
12
ACCUMULATOR REGISTER
OEX
3
OEM
12
OEL
12
Data present at the A and B input regis-
ters is latched on the rising edges of
CLK A and CLK B respectively. RND,
TC, ACC, and SUB controls are latched
on the rising edge of the logical OR of
CLK AandCLK B. TCspecifiestheinput
as two’s complement
(TC HIGH) or unsigned magnitude
(TC LOW). RND, when HIGH, adds ‘1’
to the most significant bit position of the
least significant half of the product. Sub-
sequent truncation of the 12 least signifi-
cant bits produces a result correctly
rounded to 12-bit precision.
The ACC and SUB inputs control accu-
mulator operation. ACC HIGH results in
addition of the multiplier product and
the accumulator contents, with the result
stored in the accumulator register on the
rising edge of CLK R. ACC and SUB
HIGH results in subtraction of the accu-
mulator contents from the multiplier
product, with the result stored in the
accumulator register. With ACC LOW
and SUB LOW, no accumulation occurs
and the next product is loaded directly
into the accumulator register. ACC LOW
and SUB HIGH is undefined.
The LMA1009/2009 output register (ac-
cumulator register) is divided into three
independently controlled sections. The
least significant result (LSR) and most
significant result (MSR) registers are 12
bits in length. The extended result regis-
ter (XTR) is 3 bits long.
Each output register has an independ-
ent output enable control. In addition
to providing control of the three-state
output buffers, when OEX, OEM, or
OEL are HIGH and PREL is HIGH, data
can be preloaded via the bidirectional
output pins into the respective output
registers. Data present on the output
pins is latched on the rising edge of
CLK R. The interrelation of PREL and
the enable controls is summarized in
Table 1.
R26-24
R23-12
R11-0
Multiplier-Accumulators
1 03/29/2000–LDS.10/2009-L
1 page  
DEVICES INCORPORATED
LMA 1009/2009
12 x 12-bit Multiplier-Accumulator
NOTES
1. Maximum Ratings indicate stress
specifications only. Functional oper-
ation of these products at values beyond
those indicated in the Operating Condi-
tions table is not implied. Exposure to
maximum rating conditions for ex-
tended periods may affect reliability.
2. The products described by this spec-
ification include internal circuitry de-
signed to protect the chip from damag-
ing substrate injection currents and ac-
cumulations of static charge. Neverthe-
less, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to
avoid exposure to excessive electrical
stress values.
3. Thisdeviceprovideshardclampingof
transient undershoot and overshoot. In-
put levels below ground or above VCC
will be clamped beginning at –0.6 V and
VCC + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of –0.5 V to +7.0 V. Device opera-
tion will not be adversely affected, how-
ever, input current levels will be well in
excess of 100 mA.
4. Actual test conditions may vary from
those designated but operation is guar-
anteed as specified.
5. Supply current for a given applica-
tion can be accurately approximated by:
where
NCV2 F
4
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing ev-
ery cycle and no load, at a 5 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
VCC or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tDIS test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified IOH and IOL at an output
voltage of VOH min and VOL max
respectively. Alternatively, a diode
bridge with upper and lower current
sources of IOH and IOL respectively,
and a balancing voltage of 1.5 V may be
used. Parasitic capacitance is 30 pF
minimum, and may be distributed.
This device has high-speed outputs ca-
pable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:
a. A 0.1 µF ceramic capacitor should be
installed between VCC and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
should be installed between device VCC
and the tester common, and device
ground and tester common.
b. Ground and VCC supply planes
must be brought directly to the DUT
socket or contactor fingers.
c. Input voltages should be adjusted to
compensate for inductive ground and VCC
noise to maintain required DUT input
levels relative to the DUT ground pin.
10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirements of all parts. Responses from
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. For the tENA test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the tDIS test,
the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing volt-
age, VTH, is set at 3.5 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Z-
to-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
FIGURE A. OUTPUT LOADING CIRCUIT
S1
DUT
CL
IOL
VTH
IOH
FIGURE B. THRESHOLD LEVELS
tENA
tDIS
OE 1.5 V
1.5 V
Z0
1.5 V
VOL* 0.2 V
3.5V Vth
0Z
Z1
1.5 V
VOH* 0.2 V
1Z
0V Vth
VOL* Measured VOL with IOH = –10mA and IOL = 10mA
VOH* Measured VOH with IOH = –10mA and IOL = 10mA
Multiplier-Accumulators
5 03/29/2000–LDS.10/2009-L
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet LMA2009JC45.PDF ] | |
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