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PDF PHD3055E Data sheet ( Hoja de datos )

Número de pieza PHD3055E
Descripción N-channel TrenchMOS transistor
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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Philips Semiconductors
PowerMOS transistor
Product specification
PHD3055E
GENERAL DESCRIPTION
N-channel enhancement mode
field-effect power transistor in a
plastic envelope suitable for surface
mounting featuring high avalanche
energy capability, stable blocking
voltage, fast switching and high
thermal cycling performance with low
thermal resistance. Intended for use
in Switched Mode Power Supplies
(SMPS), motor control circuits and
general purpose switching
applications.
QUICK REFERENCE DATA
SYMBOL PARAMETER
VDS
ID
Ptot
RDS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Drain-source on-state resistance
MAX.
60
12
50
0.15
UNIT
V
A
W
PINNING - SOT428
PIN DESCRIPTION
1 gate
2 drain
3 source
tab drain
PIN CONFIGURATION
tab
2
13
SYMBOL
d
g
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
ID Continuous drain current
IDM
PD
PD/Tmb
VGS
EAS
IAS
Pulsed drain current
Total dissipation
Linear derating factor
Gate-source voltage
Single pulse avalanche
energy
Peak avalanche current
Tj, Tstg
Operating junction and
storage temperature range
Tmb = 25 ˚C; VGS = 10 V
Tmb = 100 ˚C; VGS = 10 V
Tmb = 25 ˚C
Tmb = 25 ˚C
Tmb > 25 ˚C
VDD 50 V; starting Tj = 25˚C; RGS = 50 ;
VGS = 10 V
VDD 50 V; starting Tj = 25˚C; RGS = 50 ;
VGS = 10 V
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
12
9
48
50
0.33
± 30
25
6
175
UNIT
A
A
A
W
W/K
V
mJ
A
˚C
THERMAL RESISTANCES
SYMBOL
Rth j-mb
Rth j-a
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
pcb mounted, minimum
footprint
TYP.
-
50
MAX.
3
-
UNIT
K/W
K/W
September 1997
1
Rev 1.000

1 page




PHD3055E pdf
Philips Semiconductors
PowerMOS transistor
Product specification
PHD3055E
VGS, Gate-Source voltage (Volts)
15
ID = 10 A
Tj = 25 C
VDS = 30 V
10
PHP3055E
48 V
5
0
0 5 10 15
Qg, Gate charge (nC)
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); parameter VDS
Switching times (ns)
1000
VDD = 30 V
VGS = 10 V
RD = 2.7 Ohms
ID = 10 A
100 Tj = 25 C
tr
td(off)
tf
10
td(on)
PHP3055E
1
0 20 40 60 80
RG, Gate resistance (Ohms)
Fig.14. Typical switching times.
td(on), tr, td(off), tf = f(RG)
100
Normalised Drain-source breakdown voltage
1.15
V(BR)DSS @ Tj
V(BR)DSS @ 25 C
1.1
1.05
1
0.95
0.9
0.85
-100
-50 0 50 100
Tj, Junction temperature (C)
150
Fig.15. Normalised drain-source breakdown voltage.
V(BR)DSS/V(BR)DSS 25 ˚C = f(Tj)
IF, Source-drain diode current (Amps)
20
VGS = 0 V
PHP3055E
15
Tj = 175 C
Tj = 25 C
10
5
0
0 0.5 1
VSDS, Source-drain voltage (Volts)
1.5
Fig.16. Source-Drain diode characteristic.
IF = f(VSDS); parameter Tj
EAS, Normalised unclamped inductive energy (%)
120
110
100
90
80
70
60
50
40
30
20
10
0
20 40 60 80 100 120 140 160 180
Starting Tj ( C)
Fig.17. Normalised unclamped inductive energy.
EAS% = f(Tj)
VGS
0
RGS
L
VDS
T.U.T.
+ VDD
-
-ID/100
R 01
shunt
Fig.18. Unclamped inductive test circuit.
EAS = 0.5 LID2 V(BR)DSS/(V(BR)DSS VDD)
September 1997
5
Rev 1.000

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