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PDF MCF5470 Data sheet ( Hoja de datos )
| Número de pieza | MCF5470 | |
| Descripción | MCF547x Integrated Microprocessor Electrical Characteristics | |
| Fabricantes | ETC | |
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Freescale Semiconductor
Data Sheet
MCF5475EC
Rev. 2, 10/2004
MCF547x Integrated
Microprocessor Electrical
Characteristics
Applies to the MCF5470, MCF5471, MCF5472, MCF5473,
MCF5474, and MCF5475
This chapter contains electrical specification tables and
reference timing diagrams for the MCF547x
microprocessor. This section contains detailed
information on power considerations, DC/AC electrical
characteristics, and AC timing specifications of the
MCF547x.
NOTE
The parameters specified
in this MPU document
supersede any values
found in the module
specifications.
1 Maximum Ratings
Table of Contents
1 Maximum Ratings................................................1
2 Thermal Characteristics ......................................2
3 DC Electrical Specifications ................................3
4 Supply Voltage Sequencing and Separation
Cautions ..............................................................5
5 Output Driver Capability and Loading .................6
6 PLL Timing Specifications ...................................7
7 Reset Timing Specifications ................................8
8 FlexBus................................................................8
9 SDRAM Bus ......................................................11
10 PCI Bus .............................................................17
11 Fast Ethernet AC Timing Specifications ............18
12 General Timing Specifications...........................21
13 I2C Input/Output Timing Specifications .............21
14 JTAG and Boundary Scan Timing .....................23
15 DSPI Electrical Specifications ...........................26
16 Timer Module AC Timing Specifications............26
Table 1 lists maximum and minimum ratings for supply
and operating voltages and storage temperature.
Operating outside of these ranges may cause erratic
behavior or damage to the processor.
© Freescale Semiconductor, Inc., 2004. All rights reserved.
1 page  
Supply Voltage Sequencing and Separation Cautions
4 Supply Voltage Sequencing and Separation
Cautions
Figure 3 shows situations in sequencing the I/O VDD (EVDD), SDRAM VDD (SD VDD), PLL VDD (PLL
VDD), and Core VDD (IVDD).
3.3V
2.5V
1.5V
1
Supplies Stable
EVDD, SD VDD (3.3V)
SD VDD (2.5V)
IVDD, PLL VDD
2
0
NOTES:
Time
1. IVDD should not exceed EVDD, SD VDD or PLL VDD by more than
0.4V at any time, including power-up.
2. Recommended that IVDD/PLL VDD should track EVDD/SD VDD up to
0.9V, then separate for completion of ramps.
3. Input voltage must not be greater than the supply voltage (EVDD, SD VDD,
IVDD, or PLL VDD) by more than 0.5V at any time, including during power-up.
4. Use 1 microsecond or slower rise time for all supplies.
Figure 3. Supply Voltage Sequencing and Separation Cautions
The relationship between SD VDD and EVDD is non-critical during power-up and power-down sequences.
Both SD VDD (2.5V or 3.3V) and EVDD are specified relative to IVDD.
4.1 Power Up Sequence
If EVDD/SD VDD are powered up with the IVDD at 0V, then the sense circuits in the I/O pads will cause
all pad output drivers connected to the EVDD/SD VDD to be in a high impedance state. There is no limit
on how long after EVDD/SD VDD powers up before IVDD must power up. IVDD should not lead the EVDD,
SD VDD or PLL VDD by more than 0.4V during power ramp up, or there will be high current in the internal
ESD protection diodes. The rise times on the power supplies should be slower than 1 microsecond to avoid
turning on the internal ESD protection clamp diodes.
MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2
Freescale Semiconductor
5
5 Page 
CLKIN
AD[X:0]
AD[31:Y]
R/W
ALE
TSIZ[1:0]
FBCSn, BE/BWEn
OE
TA
FB1
FB2
A[31:Y]
A[X:0]
DATA
FB3
FB3
TSIZ[1:0]
FB7
FB6
Figure 7. FlexBus Write Timing
SDRAM Bus
9 SDRAM Bus
The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports
either standard SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time.
The SDRAM controller uses SSTL2 and SSTL3 I/O drivers. Both SSTL drive modes are programmable
for either Class I or Class II drive strength.
9.1 SDR SDRAM AC Timing Characteristics
The following timing numbers indicate when data will be latched or driven onto the external bus, relative
to the memory bus clock, when operating in SDR mode on write cycles and relative to SDR_DQS on read
cycles. The MCF547x SDRAM controller is a DDR controller that has an SDR mode. Because it is
designed to support DDR, a DQS pulse must still be supplied to the MCF547x for each data beat of an
SDR read. The MCF547x accomplishes this by asserting a signal called SDR_DQS during read cycles.
Care must be taken during board design to adhere to the following guidelines and specs with regard to the
SDR_DQS signal and its usage.
MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2
Freescale Semiconductor
11
11 Page | ||
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| PDF Descargar | [ Datasheet MCF5470.PDF ] | |
Hoja de datos destacado
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