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PDF RTH010 Data sheet ( Hoja de datos )
| Número de pieza | RTH010 | |
| Descripción | 9-Ghz Bandwidth 1 Gs/s Dual Track-and-Hold | |
| Fabricantes | Rockwell | |
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RTH010 DATA SHEET REV F
RTH010
9 GHz Bandwidth 1 GS/s Dual Track-and-Hold
Features
♦ 9 GHz Small-Signal Input Bandwidth
♦ 6 GHz Large-Signal Input Bandwidth (1 Vpp)
♦ 200 - 1000 MHz Sampling Rate
♦ -63 dB Hold Mode Distortion (0.5 GHz 1 Vpp VIN)
♦ -59 dB Hold Mode Distortion (1.0 GHz 1 Vpp VIN)
♦ -45 dB Hold Mode Distortion (3.0 GHz 0.5 Vpp VIN)
♦ < 100 fs Aperture Jitter
♦ < 250 ps Acquisition Time
♦ < 50 ps Rise Time (20 – 80%)
♦ Differential Analog Input/Output
♦ 100 – 1000 MHz Output Data Rate
♦ Output Held more than Half Clock Cycle
♦ Track Mode Select
Applications
♦ Test Instrumentation Equipment
♦ RF Demodulation Systems
♦ Radar
♦ Software Radio
♦ Digital Receiver Systems
♦ High-Speed DAC Deglitching
♦ THA for Differential ADCs
♦ Digital Sampling Oscilloscopes
Figure 1. Functional Diagram
Product Description
RTH010’s unprecedented bandwidth and
aperture jitter enable 10-bit 1-GS/s sampling of
DC to multi-GHz signals. The differential-to-
differential dual track-and-hold cascades two
track-and-hold circuits, TH1 and TH2. It is a
monolithic circuit fabricated in an 80-GHz fT
GaAs HBT process. The RTH010 provides a
held output for more than half a clock cycle,
easing bandwidth requirements of subsequent
circuitry relative to the case of a single track-
and-hold (TH). The option to independently
clock TH1 and TH2 (as low as 100 MHz) further
relaxes this requirement for sub-sampling
applications.
Absolute Maximum Ratings
Supply Voltages
VCC to GND …………………...………………. -1 V to +6 V
VEE to GND …………………....……………… -6 V to +1 V
VCC to VEE ……………………………………. -1 to +11 V
Input Voltages
INP, INN to GND …...…………………..…………-1 to +1 V
CLK1, CLK1B, CLK2, CLK2B to GND …….…. -1 to +1 V
TMS to GND …………………………………… -6 V to +1 V
Output Voltages
Vterm (Output Termination Voltage) to GND .. -2.5 to +3 V
Temperature
Operating Temperature ……..……………… -30 to +70 °C
Case Temperature …………..……………… -15 to +85 °C
Junction Temperature .………………………..….. +125 °C
Lead, Soldering (10 Seconds) .………………….. +220 °C
Storage ….…………………………………… -40 to 125 °C
The product specifications contained in this data sheet are subject to change. Rockwell Scientific Company reserves the right to make changes to its product
specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use.
Page 1
1 page  
RTH010 DATA SHEET REV F
If the underlying voltage noise mechanism of the
sampling jitter has a white spectrum, the
sampled signal will display a white noise floor as
well. In this case, the required aperture jitter, ∆t,
to achieve a certain SNR, for a full-scale
sinewave at frequency, f, is given by (B. Razavi,
Principles of Data Conversion, IEEE Press,
1995, Appendix 2.1):
SNR (dB) = −20 log(2πf∆t)
If this TH is used in front of an n-bit ADC, then
the ideal ADC SNDR is given by:
SNDR(dB) = 10log(3 / 2) + 20 log(2)n = 1.76 + 6.02n
In order that the TH jitter performance not limit
the ADC performance, the jitter must fulfill:
∆t ≤
1
6π 2n f
.
Note that this is independent of the sampling
rate, so undersampling does not improve jitter
tolerance. The averaging that is often combined
with undersampling in test equipment, does
improve jitter tolerance (and tolerance to other
white noise effects).
The criterion above is sharper than the standard
(incorrect) time-domain slope estimate by a
factor √6. The reason is that n-bit quantization
requires an rms error of (quantization step)/√12,
which is considerably smaller than the
quantization step error implicitly allowed in the
usual time-domain estimates (another √2 comes
from the energy of a sinewave relative to its
amplitude squared).
The time-domain maximum slope argument can
be appropriate for non-sinusoidal inputs, such as
those encountered in instrumentation. If the rms
error, ∆V, in the maximum slope region, slope
FSR/(rise time), is used to define an effective
number of bits, n, then the jitter simply needs to
fulfill:
∆t
≤
rise time
2n
Clock Jitter. The standard deviation of the
instants of the mid-point of the relevant (rising or
falling) edge of the clock source relative to the
ideal instants (best fit). This jitter can be derived
from the phase noise of the clock source, where
the lower frequency bound of integration should
correspond to the duration of a measurement
record that the source will be used for.
Full Scale Range (FSR). The maximum
difference between the highest and lowest input
levels for which various device performance
specifications hold, unless otherwise noted.
Gain. Ratio of output signal magnitude to input
signal magnitude. For sinewave inputs, it is the
ratio of the amplitude of the first (main) harmonic
output (HD1) to the amplitude of the input.
Input Bandwidth (BW, bw). The input
frequency at which the gain for sinewave inputs
is reduced by 3 dB (factor 1/√2) relative to its
average value at low frequencies. The low
frequency range is defined as the range
including DC over which the gain stays
essentially constant. The high frequency range
is characterized by an increase in gain variation
versus frequency, at least including the eventual
monotonic decrease of the gain (“roll-off”). The
input bandwidth tends to be input amplitude
dependent. It is normally largest for very small
inputs (small signal bandwidth, bw) and smallest
for FSR inputs (large signal bandwidth, BW).
Settling Time (ts). The delay between the time
that a track-and-hold circuit (TH) enters hold
mode and the time that the TH hold capacitor
nodes settle to within some specified precision.
The settling time sets a lower limit on the
required hold time during clocked operation.
Spectrum. The finite Fourier transform (FFT) of
the discrete-time-sampled TH output. Ideally,
this is obtained with a very high-resolution ADC
quantizing the TH output with a clock rate locked
to the TH clock (the ADC may be clocked at a
slower rate than the TH). In the case of a dual
TH (DTH), we can also use the beat frequency
test, where the input frequency is close to an
integer multiple of the clock frequency, and the
DTH output is fed directly into a spectrum
analyzer. The DTH output then contains little
high frequency energy and the low frequency
part of the spectrum analyzer sweep accurately
The product specifications contained in this data sheet are subject to change. Rockwell Scientific Company reserves the right to make changes to its product
specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use.
Page 5
5 Page 
RTH010 DATA SHEET REV F
Package Information
The package is a 24-lead metallized ceramic-
base glass-sidewall Quad Flat-Pack. The leads
are trimmed to 0.150 inch (3.81 mm) length. The
0.275 SQ
thermal impedance (junction to base) is
approximately 15 °C/W. The lid is sealed with
epoxy.
Pin #1
0.150
0.012
0.030
0.381
Figure 10. RTH010 package outline. Dimensions shown in inches, tolerance ±0.002 inch
Ordering Information
PART NUMBER
RTH010QFP
RTH010DIE
PACKAGE TYPE
24-Lead Ceramic Quad FP
Die14
TEMPERATURE RANGE
-30 to +70 °C
0 to +100 °C
14 Die performance is as good as or better than that of the packaged part. On-wafer measurements show large/small-signal
bandwidths, BW/bw, and THD at 5-GHz 0.5-Vpp equal to 6/9.3 GHz and –42 dB vs. 6/9 GHz and –32 dB for the packaged part.
The product specifications contained in this data sheet are subject to change. Rockwell Scientific Company reserves the right to make changes to its product
specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use.
Page 11
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