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PDF MSM9225 Data sheet ( Hoja de datos )
| Número de pieza | MSM9225 | |
| Descripción | CAN (Controller Area Network) Controller | |
| Fabricantes | OKI electronic componets | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MSM9225 (archivo pdf) en la parte inferior de esta página. Total 70 Páginas | ||
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E2F0016-19-43
¡¡ SemiconSduectomr iconductor
MSM9225
CAN (Controller Area Network) Controller
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GENERAL DESCRIPTION
The MSM9225 is a microcontroller peripheral LSI which conforms to the CAN protocol for
high-speed LANs in automobiles.
FEATURES
•Conforms to CAN protocol specification (Bosch Co., V.2.0 part b/Full CAN)
• Maximum 1 Mbps real-time communication control (programmable)
• Communication system:
Transmission line is bi-directional, two-wire serial communications
NRZ (Non-Return to Zero) system using bit stuff function
Multi-master system
Broadcast system
• Maximum 16 messages ¥ 8 bytes of message buffer
Number of messages can be extended by group message function (max: 2 groups)
• Priority control by identifier
Normally 2032 types, 2032 ¥ 218 types at extension
• Microcontroller interface
Corresponding to both parallel and serial interface
Parallel interface: separate address/data bus type (with address latch signal/no
address latch signal) and multiplexed address/data bus type.
Serial interface: Synchronous communication type
Interrupt is used for three outputs: transmission/receive/error
• Error control:
Bit error/stuff error/CRC error/form error/acknowledge error detection functions
Retransmission / error status monitoring function when error occurs
• Communication control by transmission request function
• Sleep/Stop mode function
• Supply voltage: 5 V ±10%
• Operating temperature: -40 to +115˚C
• Package: 44-pin plastic QFP (QFP44-P-910-0.80-2K) (Product name: MSM9225GA-2K)
1/73
1 page  
¡ Semiconductor
MSM9225
Symbol
Pin Type
Description
Microcontroller interface select pins.
Mode1, 0 29, 30 I
Mode1 Mode0
0 0 Parallel mode
01
10
1 1 Serial mode
Interface
Separate buses No address latch signal
With address latch signal
Multiplexed buses
INT 11 O
RESET 25 I
XT 13
XT 14
RX0, RX1 18, 19
TX0, TX1 22, 23
12, 24,
VDD 40
6, 15, 21
GND
28, 39
AVDD
20
AGND
17
I
O
I
O
—
—
—
—
Interrupt request output pin.
When an interrupt request occurs, a "L" level is output.
Three types of interrupts share this pin: transmission complete, reception complete,
and error.
Reset pin.
System is reset when this pin is at a "L" level.
Clock pins. If internal oscillator is used, connect a crystal oscillator. If external
clock is input, input clock via XT pin. The XT pin should be left open.
Receive input pin. Differential amplifier included.
Transmission output pin.
Internal logic power supply pin.
Internal logic GND pin.
Power supply pin for receive input differential amplifier.
GND pin for receive input differential amplifier.
5/73
5 Page 
¡ Semiconductor
MSM9225
Adderss MSB
LSB
¥ 3h 7 6 5 4 3 2 1 0
IDB10 :
IDB11 :
IDB12 :
IDB13 :
IDB14 :
IDB15 :
IDB16 :
IDB17 :
Identifier 2
Address MSB
LSB
¥ 4h 7 6 5 4 3 2 1 0
IDB2 :
IDB3 :
IDB4 :
IDB5 :
IDB6 :
IDB7 :
IDB8 :
IDB9 :
Identifier 3
Address MSB
LSB
¥ 5h 7 6 5 4 3 2 1 0
Not used (Don't care)
Not used (Don't care)
Not used (Don't care)
Not used (Don't care)
Not used (Don't care)
Not used (Don't care)
IDB0 :
Identifier 4
IDB1 :
11/73
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet MSM9225.PDF ] | |
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